Lines Matching defs:amdgpu_crtc

381 struct amdgpu_crtc {  struct
382 	struct drm_crtc base;
383 	int crtc_id;
384 	bool enabled;
385 	bool can_tile;
386 	uint32_t crtc_offset;
387 	struct drm_gem_object *cursor_bo;
388 	uint64_t cursor_addr;
389 	int cursor_x;
390 	int cursor_y;
391 	int cursor_hot_x;
392 	int cursor_hot_y;
393 	int cursor_width;
394 	int cursor_height;
395 	int max_cursor_width;
396 	int max_cursor_height;
397 	enum amdgpu_rmx_type rmx_type;
398 	u8 h_border;
399 	u8 v_border;
400 	fixed20_12 vsc;
401 	fixed20_12 hsc;
402 	struct drm_display_mode native_mode;
403 	u32 pll_id;
405 	struct amdgpu_flip_work *pflip_works;
406 	enum amdgpu_flip_status pflip_status;
407 	int deferred_flip_completion;
409 	struct dm_irq_params dm_irq_params;
411 	struct amdgpu_atom_ss ss;
412 	bool ss_enabled;
413 	u32 adjusted_clock;
414 	int bpc;
415 	u32 pll_reference_div;
416 	u32 pll_post_div;
417 	u32 pll_flags;
418 	struct drm_encoder *encoder;
419 	struct drm_connector *connector;
421 	u32 line_time;
422 	u32 wm_low;
423 	u32 wm_high;
424 	u32 lb_vblank_lead_lines;
425 	struct drm_display_mode hw_mode;
427 	struct hrtimer vblank_timer;
428 	enum amdgpu_interrupt_state vsync_timer_enabled;
430 	int otg_inst;
431 	struct drm_pending_vblank_event *event;