Lines Matching +full:lock +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
41 raw_spinlock_t lock; member
47 static int zx_direction_input(struct gpio_chip *gc, unsigned offset) in zx_direction_input() argument
53 if (offset >= gc->ngpio) in zx_direction_input()
54 return -EINVAL; in zx_direction_input()
56 raw_spin_lock_irqsave(&chip->lock, flags); in zx_direction_input()
57 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); in zx_direction_input()
58 gpiodir &= ~BIT(offset); in zx_direction_input()
59 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); in zx_direction_input()
60 raw_spin_unlock_irqrestore(&chip->lock, flags); in zx_direction_input()
65 static int zx_direction_output(struct gpio_chip *gc, unsigned offset, in zx_direction_output() argument
72 if (offset >= gc->ngpio) in zx_direction_output()
73 return -EINVAL; in zx_direction_output()
75 raw_spin_lock_irqsave(&chip->lock, flags); in zx_direction_output()
76 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); in zx_direction_output()
77 gpiodir |= BIT(offset); in zx_direction_output()
78 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); in zx_direction_output()
81 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1); in zx_direction_output()
83 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0); in zx_direction_output()
84 raw_spin_unlock_irqrestore(&chip->lock, flags); in zx_direction_output()
89 static int zx_get_value(struct gpio_chip *gc, unsigned offset) in zx_get_value() argument
93 return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset)); in zx_get_value()
96 static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value) in zx_set_value() argument
101 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1); in zx_set_value()
103 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0); in zx_set_value()
110 int offset = irqd_to_hwirq(d); in zx_irq_type() local
113 u16 bit = BIT(offset); in zx_irq_type()
115 if (offset < 0 || offset >= ZX_GPIO_NR) in zx_irq_type()
116 return -EINVAL; in zx_irq_type()
118 raw_spin_lock_irqsave(&chip->lock, flags); in zx_irq_type()
120 gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV); in zx_irq_type()
121 gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE); in zx_irq_type()
122 gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP); in zx_irq_type()
123 gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN); in zx_irq_type()
147 writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE); in zx_irq_type()
148 writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP); in zx_irq_type()
149 writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN); in zx_irq_type()
150 writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV); in zx_irq_type()
151 raw_spin_unlock_irqrestore(&chip->lock, flags); in zx_irq_type()
159 int offset; in zx_irq_handler() local
166 pending = readw_relaxed(chip->base + ZX_GPIO_MIS); in zx_irq_handler()
167 writew_relaxed(pending, chip->base + ZX_GPIO_IC); in zx_irq_handler()
169 for_each_set_bit(offset, &pending, ZX_GPIO_NR) in zx_irq_handler()
170 generic_handle_irq(irq_find_mapping(gc->irq.domain, in zx_irq_handler()
171 offset)); in zx_irq_handler()
184 raw_spin_lock(&chip->lock); in zx_irq_mask()
185 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask; in zx_irq_mask()
186 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM); in zx_irq_mask()
187 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask; in zx_irq_mask()
188 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE); in zx_irq_mask()
189 raw_spin_unlock(&chip->lock); in zx_irq_mask()
199 raw_spin_lock(&chip->lock); in zx_irq_unmask()
200 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask; in zx_irq_unmask()
201 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM); in zx_irq_unmask()
202 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask; in zx_irq_unmask()
203 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE); in zx_irq_unmask()
204 raw_spin_unlock(&chip->lock); in zx_irq_unmask()
208 .name = "zx-gpio",
216 struct device *dev = &pdev->dev; in zx_gpio_probe()
223 return -ENOMEM; in zx_gpio_probe()
225 chip->base = devm_platform_ioremap_resource(pdev, 0); in zx_gpio_probe()
226 if (IS_ERR(chip->base)) in zx_gpio_probe()
227 return PTR_ERR(chip->base); in zx_gpio_probe()
229 id = of_alias_get_id(dev->of_node, "gpio"); in zx_gpio_probe()
231 raw_spin_lock_init(&chip->lock); in zx_gpio_probe()
232 chip->gc.request = gpiochip_generic_request; in zx_gpio_probe()
233 chip->gc.free = gpiochip_generic_free; in zx_gpio_probe()
234 chip->gc.direction_input = zx_direction_input; in zx_gpio_probe()
235 chip->gc.direction_output = zx_direction_output; in zx_gpio_probe()
236 chip->gc.get = zx_get_value; in zx_gpio_probe()
237 chip->gc.set = zx_set_value; in zx_gpio_probe()
238 chip->gc.base = ZX_GPIO_NR * id; in zx_gpio_probe()
239 chip->gc.ngpio = ZX_GPIO_NR; in zx_gpio_probe()
240 chip->gc.label = dev_name(dev); in zx_gpio_probe()
241 chip->gc.parent = dev; in zx_gpio_probe()
242 chip->gc.owner = THIS_MODULE; in zx_gpio_probe()
247 writew_relaxed(0xffff, chip->base + ZX_GPIO_IM); in zx_gpio_probe()
248 writew_relaxed(0, chip->base + ZX_GPIO_IE); in zx_gpio_probe()
252 girq = &chip->gc.irq; in zx_gpio_probe()
253 girq->chip = &zx_irqchip; in zx_gpio_probe()
254 girq->parent_handler = zx_irq_handler; in zx_gpio_probe()
255 girq->num_parents = 1; in zx_gpio_probe()
256 girq->parents = devm_kcalloc(&pdev->dev, 1, in zx_gpio_probe()
257 sizeof(*girq->parents), in zx_gpio_probe()
259 if (!girq->parents) in zx_gpio_probe()
260 return -ENOMEM; in zx_gpio_probe()
261 girq->parents[0] = irq; in zx_gpio_probe()
262 girq->default_type = IRQ_TYPE_NONE; in zx_gpio_probe()
263 girq->handler = handle_simple_irq; in zx_gpio_probe()
265 ret = gpiochip_add_data(&chip->gc, chip); in zx_gpio_probe()
277 .compatible = "zte,zx296702-gpio",