228 	u16 mask;  in vr41xx_set_irq_trigger()  local
231 		mask = 1 << pin;  in vr41xx_set_irq_trigger()
233 			giu_set(GIUINTTYPL, mask);  in vr41xx_set_irq_trigger()
235 				giu_set(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
237 				giu_clear(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
241 					giu_set(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
242 					giu_clear(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
245 					giu_clear(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
246 					giu_set(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
249 					giu_set(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
250 					giu_set(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
258 			giu_clear(GIUINTTYPL, mask);  in vr41xx_set_irq_trigger()
259 			giu_clear(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
264 		giu_write(GIUINTSTATL, mask);  in vr41xx_set_irq_trigger()
266 		mask = 1 << (pin - GIUINT_HIGH_OFFSET);  in vr41xx_set_irq_trigger()
268 			giu_set(GIUINTTYPH, mask);  in vr41xx_set_irq_trigger()
270 				giu_set(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
272 				giu_clear(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
276 					giu_set(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
277 					giu_clear(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
280 					giu_clear(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
281 					giu_set(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
284 					giu_set(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
285 					giu_set(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
293 			giu_clear(GIUINTTYPH, mask);  in vr41xx_set_irq_trigger()
294 			giu_clear(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
299 		giu_write(GIUINTSTATH, mask);  in vr41xx_set_irq_trigger()
306 	u16 mask;  in vr41xx_set_irq_level()  local
309 		mask = 1 << pin;  in vr41xx_set_irq_level()
311 			giu_set(GIUINTALSELL, mask);  in vr41xx_set_irq_level()
313 			giu_clear(GIUINTALSELL, mask);  in vr41xx_set_irq_level()
314 		giu_write(GIUINTSTATL, mask);  in vr41xx_set_irq_level()
316 		mask = 1 << (pin - GIUINT_HIGH_OFFSET);  in vr41xx_set_irq_level()
318 			giu_set(GIUINTALSELH, mask);  in vr41xx_set_irq_level()
320 			giu_clear(GIUINTALSELH, mask);  in vr41xx_set_irq_level()
321 		giu_write(GIUINTSTATH, mask);  in vr41xx_set_irq_level()
328 	u16 offset, mask, reg;  in giu_set_direction()  local
336 		mask = 1 << pin;  in giu_set_direction()
339 		mask = 1 << (pin - 16);  in giu_set_direction()
343 			mask = 1 << (pin - 32);  in giu_set_direction()
348 				mask = PIOEN0;  in giu_set_direction()
352 				mask = PIOEN1;  in giu_set_direction()
364 		reg |= mask;  in giu_set_direction()
366 		reg &= ~mask;  in giu_set_direction()
376 	u16 reg, mask;  in vr41xx_gpio_get()  local
383 		mask = 1 << pin;  in vr41xx_gpio_get()
386 		mask = 1 << (pin - 16);  in vr41xx_gpio_get()
389 		mask = 1 << (pin - 32);  in vr41xx_gpio_get()
392 		mask = 1 << (pin - 48);  in vr41xx_gpio_get()
395 	if (reg & mask)  in vr41xx_gpio_get()
404 	u16 offset, mask, reg;  in vr41xx_gpio_set()  local
412 		mask = 1 << pin;  in vr41xx_gpio_set()
415 		mask = 1 << (pin - 16);  in vr41xx_gpio_set()
418 		mask = 1 << (pin - 32);  in vr41xx_gpio_set()
421 		mask = 1 << (pin - 48);  in vr41xx_gpio_set()
428 		reg |= mask;  in vr41xx_gpio_set()
430 		reg &= ~mask;  in vr41xx_gpio_set()