2  * SPEAr platform SPI chipselect abstraction over gpiolib
24  * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
25  * through system registers. This register lies outside spi (pl022)
28  * It provides control for spi chip select lines so that any chipselect
34  * struct spear_spics - represents spi chip select control
38  * @cs_value_bit: bit to program high or low chipselect
41  * @use_count: use count of a spi controller cs lines
60 	return -ENXIO;  in spics_get_value()
69 	tmp = readl_relaxed(spics->base + spics->perip_cfg);  in spics_set_value()
70 	if (spics->last_off != offset) {  in spics_set_value()
71 		spics->last_off = offset;  in spics_set_value()
72 		tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift);  in spics_set_value()
73 		tmp |= offset << spics->cs_enable_shift;  in spics_set_value()
77 	tmp &= ~(0x1 << spics->cs_value_bit);  in spics_set_value()
78 	tmp |= value << spics->cs_value_bit;  in spics_set_value()
79 	writel_relaxed(tmp, spics->base + spics->perip_cfg);  in spics_set_value()
84 	return -ENXIO;  in spics_direction_input()
99 	if (!spics->use_count++) {  in spics_request()
100 		tmp = readl_relaxed(spics->base + spics->perip_cfg);  in spics_request()
101 		tmp |= 0x1 << spics->sw_enable_bit;  in spics_request()
102 		tmp |= 0x1 << spics->cs_value_bit;  in spics_request()
103 		writel_relaxed(tmp, spics->base + spics->perip_cfg);  in spics_request()
114 	if (!--spics->use_count) {  in spics_free()
115 		tmp = readl_relaxed(spics->base + spics->perip_cfg);  in spics_free()
116 		tmp &= ~(0x1 << spics->sw_enable_bit);  in spics_free()
117 		writel_relaxed(tmp, spics->base + spics->perip_cfg);  in spics_free()
123 	struct device_node *np = pdev->dev.of_node;  in spics_gpio_probe()
127 	spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL);  in spics_gpio_probe()
129 		return -ENOMEM;  in spics_gpio_probe()
131 	spics->base = devm_platform_ioremap_resource(pdev, 0);  in spics_gpio_probe()
132 	if (IS_ERR(spics->base))  in spics_gpio_probe()
133 		return PTR_ERR(spics->base);  in spics_gpio_probe()
135 	if (of_property_read_u32(np, "st-spics,peripcfg-reg",  in spics_gpio_probe()
136 				&spics->perip_cfg))  in spics_gpio_probe()
138 	if (of_property_read_u32(np, "st-spics,sw-enable-bit",  in spics_gpio_probe()
139 				&spics->sw_enable_bit))  in spics_gpio_probe()
141 	if (of_property_read_u32(np, "st-spics,cs-value-bit",  in spics_gpio_probe()
142 				&spics->cs_value_bit))  in spics_gpio_probe()
144 	if (of_property_read_u32(np, "st-spics,cs-enable-mask",  in spics_gpio_probe()
145 				&spics->cs_enable_mask))  in spics_gpio_probe()
147 	if (of_property_read_u32(np, "st-spics,cs-enable-shift",  in spics_gpio_probe()
148 				&spics->cs_enable_shift))  in spics_gpio_probe()
153 	spics->chip.ngpio = NUM_OF_GPIO;  in spics_gpio_probe()
154 	spics->chip.base = -1;  in spics_gpio_probe()
155 	spics->chip.request = spics_request;  in spics_gpio_probe()
156 	spics->chip.free = spics_free;  in spics_gpio_probe()
157 	spics->chip.direction_input = spics_direction_input;  in spics_gpio_probe()
158 	spics->chip.direction_output = spics_direction_output;  in spics_gpio_probe()
159 	spics->chip.get = spics_get_value;  in spics_gpio_probe()
160 	spics->chip.set = spics_set_value;  in spics_gpio_probe()
161 	spics->chip.label = dev_name(&pdev->dev);  in spics_gpio_probe()
162 	spics->chip.parent = &pdev->dev;  in spics_gpio_probe()
163 	spics->chip.owner = THIS_MODULE;  in spics_gpio_probe()
164 	spics->last_off = -1;  in spics_gpio_probe()
166 	ret = devm_gpiochip_add_data(&pdev->dev, &spics->chip, spics);  in spics_gpio_probe()
168 		dev_err(&pdev->dev, "unable to add gpio chip\n");  in spics_gpio_probe()
172 	dev_info(&pdev->dev, "spear spics registered\n");  in spics_gpio_probe()
176 	dev_err(&pdev->dev, "DT probe failed\n");  in spics_gpio_probe()
177 	return -EINVAL;  in spics_gpio_probe()
181 	{ .compatible = "st,spear-spics-gpio" },
188 		.name = "spear-spics-gpio",