1 // SPDX-License-Identifier: GPL-2.0-only
51 	raw_spinlock_t		lock;  member
63 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)  in pl061_get_direction()  argument
67 	if (readb(pl061->base + GPIODIR) & BIT(offset))  in pl061_get_direction()
73 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)  in pl061_direction_input()  argument
79 	raw_spin_lock_irqsave(&pl061->lock, flags);  in pl061_direction_input()
80 	gpiodir = readb(pl061->base + GPIODIR);  in pl061_direction_input()
81 	gpiodir &= ~(BIT(offset));  in pl061_direction_input()
82 	writeb(gpiodir, pl061->base + GPIODIR);  in pl061_direction_input()
83 	raw_spin_unlock_irqrestore(&pl061->lock, flags);  in pl061_direction_input()
88 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,  in pl061_direction_output()  argument
95 	raw_spin_lock_irqsave(&pl061->lock, flags);  in pl061_direction_output()
96 	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));  in pl061_direction_output()
97 	gpiodir = readb(pl061->base + GPIODIR);  in pl061_direction_output()
98 	gpiodir |= BIT(offset);  in pl061_direction_output()
99 	writeb(gpiodir, pl061->base + GPIODIR);  in pl061_direction_output()
105 	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));  in pl061_direction_output()
106 	raw_spin_unlock_irqrestore(&pl061->lock, flags);  in pl061_direction_output()
111 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)  in pl061_get_value()  argument
115 	return !!readb(pl061->base + (BIT(offset + 2)));  in pl061_get_value()
118 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)  in pl061_set_value()  argument
122 	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));  in pl061_set_value()
129 	int offset = irqd_to_hwirq(d);  in pl061_irq_type()  local
132 	u8 bit = BIT(offset);  in pl061_irq_type()
134 	if (offset < 0 || offset >= PL061_GPIO_NR)  in pl061_irq_type()
135 		return -EINVAL;  in pl061_irq_type()
140 		dev_err(gc->parent,  in pl061_irq_type()
143 			offset);  in pl061_irq_type()
144 		return -EINVAL;  in pl061_irq_type()
148 	raw_spin_lock_irqsave(&pl061->lock, flags);  in pl061_irq_type()
150 	gpioiev = readb(pl061->base + GPIOIEV);  in pl061_irq_type()
151 	gpiois = readb(pl061->base + GPIOIS);  in pl061_irq_type()
152 	gpioibe = readb(pl061->base + GPIOIBE);  in pl061_irq_type()
167 		dev_dbg(gc->parent, "line %d: IRQ on %s level\n",  in pl061_irq_type()
168 			offset,  in pl061_irq_type()
176 		dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);  in pl061_irq_type()
191 		dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",  in pl061_irq_type()
192 			offset,  in pl061_irq_type()
200 		dev_warn(gc->parent, "no trigger selected for line %d\n",  in pl061_irq_type()
201 			 offset);  in pl061_irq_type()
204 	writeb(gpiois, pl061->base + GPIOIS);  in pl061_irq_type()
205 	writeb(gpioibe, pl061->base + GPIOIBE);  in pl061_irq_type()
206 	writeb(gpioiev, pl061->base + GPIOIEV);  in pl061_irq_type()
208 	raw_spin_unlock_irqrestore(&pl061->lock, flags);  in pl061_irq_type()
216 	int offset;  in pl061_irq_handler()  local
223 	pending = readb(pl061->base + GPIOMIS);  in pl061_irq_handler()
225 		for_each_set_bit(offset, &pending, PL061_GPIO_NR)  in pl061_irq_handler()
226 			generic_handle_irq(irq_find_mapping(gc->irq.domain,  in pl061_irq_handler()
227 							    offset));  in pl061_irq_handler()
240 	raw_spin_lock(&pl061->lock);  in pl061_irq_mask()
241 	gpioie = readb(pl061->base + GPIOIE) & ~mask;  in pl061_irq_mask()
242 	writeb(gpioie, pl061->base + GPIOIE);  in pl061_irq_mask()
243 	raw_spin_unlock(&pl061->lock);  in pl061_irq_mask()
253 	raw_spin_lock(&pl061->lock);  in pl061_irq_unmask()
254 	gpioie = readb(pl061->base + GPIOIE) | mask;  in pl061_irq_unmask()
255 	writeb(gpioie, pl061->base + GPIOIE);  in pl061_irq_unmask()
256 	raw_spin_unlock(&pl061->lock);  in pl061_irq_unmask()
260  * pl061_irq_ack() - ACK an edge IRQ
264  * in the GPIOIC (interrupt-clear) register. For level IRQs this is
273 	raw_spin_lock(&pl061->lock);  in pl061_irq_ack()
274 	writeb(mask, pl061->base + GPIOIC);  in pl061_irq_ack()
275 	raw_spin_unlock(&pl061->lock);  in pl061_irq_ack()
283 	return irq_set_irq_wake(pl061->parent_irq, state);  in pl061_irq_set_wake()
288 	struct device *dev = &adev->dev;  in pl061_probe()
295 		return -ENOMEM;  in pl061_probe()
297 	pl061->base = devm_ioremap_resource(dev, &adev->res);  in pl061_probe()
298 	if (IS_ERR(pl061->base))  in pl061_probe()
299 		return PTR_ERR(pl061->base);  in pl061_probe()
301 	raw_spin_lock_init(&pl061->lock);  in pl061_probe()
302 	pl061->gc.request = gpiochip_generic_request;  in pl061_probe()
303 	pl061->gc.free = gpiochip_generic_free;  in pl061_probe()
304 	pl061->gc.base = -1;  in pl061_probe()
305 	pl061->gc.get_direction = pl061_get_direction;  in pl061_probe()
306 	pl061->gc.direction_input = pl061_direction_input;  in pl061_probe()
307 	pl061->gc.direction_output = pl061_direction_output;  in pl061_probe()
308 	pl061->gc.get = pl061_get_value;  in pl061_probe()
309 	pl061->gc.set = pl061_set_value;  in pl061_probe()
310 	pl061->gc.ngpio = PL061_GPIO_NR;  in pl061_probe()
311 	pl061->gc.label = dev_name(dev);  in pl061_probe()
312 	pl061->gc.parent = dev;  in pl061_probe()
313 	pl061->gc.owner = THIS_MODULE;  in pl061_probe()
318 	pl061->irq_chip.name = dev_name(dev);  in pl061_probe()
319 	pl061->irq_chip.irq_ack	= pl061_irq_ack;  in pl061_probe()
320 	pl061->irq_chip.irq_mask = pl061_irq_mask;  in pl061_probe()
321 	pl061->irq_chip.irq_unmask = pl061_irq_unmask;  in pl061_probe()
322 	pl061->irq_chip.irq_set_type = pl061_irq_type;  in pl061_probe()
323 	pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;  in pl061_probe()
325 	writeb(0, pl061->base + GPIOIE); /* disable irqs */  in pl061_probe()
326 	irq = adev->irq[0];  in pl061_probe()
328 		dev_warn(&adev->dev, "IRQ support disabled\n");  in pl061_probe()
329 	pl061->parent_irq = irq;  in pl061_probe()
331 	girq = &pl061->gc.irq;  in pl061_probe()
332 	girq->chip = &pl061->irq_chip;  in pl061_probe()
333 	girq->parent_handler = pl061_irq_handler;  in pl061_probe()
334 	girq->num_parents = 1;  in pl061_probe()
335 	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),  in pl061_probe()
337 	if (!girq->parents)  in pl061_probe()
338 		return -ENOMEM;  in pl061_probe()
339 	girq->parents[0] = irq;  in pl061_probe()
340 	girq->default_type = IRQ_TYPE_NONE;  in pl061_probe()
341 	girq->handler = handle_bad_irq;  in pl061_probe()
343 	ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);  in pl061_probe()
357 	int offset;  in pl061_suspend()  local
359 	pl061->csave_regs.gpio_data = 0;  in pl061_suspend()
360 	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);  in pl061_suspend()
361 	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);  in pl061_suspend()
362 	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);  in pl061_suspend()
363 	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);  in pl061_suspend()
364 	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);  in pl061_suspend()
366 	for (offset = 0; offset < PL061_GPIO_NR; offset++) {  in pl061_suspend()
367 		if (pl061->csave_regs.gpio_dir & (BIT(offset)))  in pl061_suspend()
368 			pl061->csave_regs.gpio_data |=  in pl061_suspend()
369 				pl061_get_value(&pl061->gc, offset) << offset;  in pl061_suspend()
378 	int offset;  in pl061_resume()  local
380 	for (offset = 0; offset < PL061_GPIO_NR; offset++) {  in pl061_resume()
381 		if (pl061->csave_regs.gpio_dir & (BIT(offset)))  in pl061_resume()
382 			pl061_direction_output(&pl061->gc, offset,  in pl061_resume()
383 					pl061->csave_regs.gpio_data &  in pl061_resume()
384 					(BIT(offset)));  in pl061_resume()
386 			pl061_direction_input(&pl061->gc, offset);  in pl061_resume()
389 	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);  in pl061_resume()
390 	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);  in pl061_resume()
391 	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);  in pl061_resume()
392 	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);  in pl061_resume()