Lines Matching +full:lock +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES PCIe-IDIO-24 family
15 * This driver supports the following ACCES devices: PCIe-IDIO-24,
16 * PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12.
58 * 23: Built-In Self-Test (BIST) Interrupt Active
73 * struct idio_24_gpio_reg - GPIO device registers structure
74 * @out0_7: Read: FET Outputs 0-7
75 * Write: FET Outputs 0-7
76 * @out8_15: Read: FET Outputs 8-15
77 * Write: FET Outputs 8-15
78 * @out16_23: Read: FET Outputs 16-23
79 * Write: FET Outputs 16-23
80 * @ttl_out0_7: Read: TTL/CMOS Outputs 0-7
81 * Write: TTL/CMOS Outputs 0-7
82 * @in0_7: Read: Isolated Inputs 0-7
84 * @in8_15: Read: Isolated Inputs 8-15
86 * @in16_23: Read: Isolated Inputs 16-23
88 * @ttl_in0_7: Read: TTL/CMOS Inputs 0-7
90 * @cos0_7: Read: COS Status Inputs 0-7
91 * Write: COS Clear Inputs 0-7
92 * @cos8_15: Read: COS Status Inputs 8-15
93 * Write: COS Clear Inputs 8-15
94 * @cos16_23: Read: COS Status Inputs 16-23
95 * Write: COS Clear Inputs 16-23
96 * @cos_ttl0_7: Read: COS Status TTL/CMOS 0-7
97 * Write: COS Clear TTL/CMOS 0-7
127 * struct idio_24_gpio - GPIO device private data structure
129 * @lock: synchronization lock to prevent I/O race conditions
130 * @reg: I/O address offset for the GPIO device registers
135 raw_spinlock_t lock; member
142 unsigned int offset) in idio_24_gpio_get_direction() argument
148 if (offset < 24) in idio_24_gpio_get_direction()
152 if (offset < 48) in idio_24_gpio_get_direction()
157 if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) in idio_24_gpio_get_direction()
164 unsigned int offset) in idio_24_gpio_direction_input() argument
172 if (offset > 47) { in idio_24_gpio_direction_input()
173 raw_spin_lock_irqsave(&idio24gpio->lock, flags); in idio_24_gpio_direction_input()
176 ctl_state = ioread8(&idio24gpio->reg->ctl) & ~out_mode_mask; in idio_24_gpio_direction_input()
177 iowrite8(ctl_state, &idio24gpio->reg->ctl); in idio_24_gpio_direction_input()
179 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); in idio_24_gpio_direction_input()
186 unsigned int offset, int value) in idio_24_gpio_direction_output() argument
194 if (offset > 47) { in idio_24_gpio_direction_output()
195 raw_spin_lock_irqsave(&idio24gpio->lock, flags); in idio_24_gpio_direction_output()
198 ctl_state = ioread8(&idio24gpio->reg->ctl) | out_mode_mask; in idio_24_gpio_direction_output()
199 iowrite8(ctl_state, &idio24gpio->reg->ctl); in idio_24_gpio_direction_output()
201 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); in idio_24_gpio_direction_output()
204 chip->set(chip, offset, value); in idio_24_gpio_direction_output()
208 static int idio_24_gpio_get(struct gpio_chip *chip, unsigned int offset) in idio_24_gpio_get() argument
211 const unsigned long offset_mask = BIT(offset % 8); in idio_24_gpio_get()
215 if (offset < 8) in idio_24_gpio_get()
216 return !!(ioread8(&idio24gpio->reg->out0_7) & offset_mask); in idio_24_gpio_get()
218 if (offset < 16) in idio_24_gpio_get()
219 return !!(ioread8(&idio24gpio->reg->out8_15) & offset_mask); in idio_24_gpio_get()
221 if (offset < 24) in idio_24_gpio_get()
222 return !!(ioread8(&idio24gpio->reg->out16_23) & offset_mask); in idio_24_gpio_get()
225 if (offset < 32) in idio_24_gpio_get()
226 return !!(ioread8(&idio24gpio->reg->in0_7) & offset_mask); in idio_24_gpio_get()
228 if (offset < 40) in idio_24_gpio_get()
229 return !!(ioread8(&idio24gpio->reg->in8_15) & offset_mask); in idio_24_gpio_get()
231 if (offset < 48) in idio_24_gpio_get()
232 return !!(ioread8(&idio24gpio->reg->in16_23) & offset_mask); in idio_24_gpio_get()
235 if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) in idio_24_gpio_get()
236 return !!(ioread8(&idio24gpio->reg->ttl_out0_7) & offset_mask); in idio_24_gpio_get()
239 return !!(ioread8(&idio24gpio->reg->ttl_in0_7) & offset_mask); in idio_24_gpio_get()
246 unsigned long offset; in idio_24_gpio_get_multiple() local
249 &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15, in idio_24_gpio_get_multiple()
250 &idio24gpio->reg->out16_23, &idio24gpio->reg->in0_7, in idio_24_gpio_get_multiple()
251 &idio24gpio->reg->in8_15, &idio24gpio->reg->in16_23, in idio_24_gpio_get_multiple()
258 bitmap_zero(bits, chip->ngpio); in idio_24_gpio_get_multiple()
260 for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { in idio_24_gpio_get_multiple()
261 index = offset / 8; in idio_24_gpio_get_multiple()
266 else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) in idio_24_gpio_get_multiple()
267 port_state = ioread8(&idio24gpio->reg->ttl_out0_7); in idio_24_gpio_get_multiple()
269 port_state = ioread8(&idio24gpio->reg->ttl_in0_7); in idio_24_gpio_get_multiple()
273 bitmap_set_value8(bits, port_state, offset); in idio_24_gpio_get_multiple()
279 static void idio_24_gpio_set(struct gpio_chip *chip, unsigned int offset, in idio_24_gpio_set() argument
285 const unsigned int mask = BIT(offset % 8); in idio_24_gpio_set()
290 if (offset > 23 && offset < 48) in idio_24_gpio_set()
294 if (offset > 47 && !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask)) in idio_24_gpio_set()
298 if (offset > 47) in idio_24_gpio_set()
299 base = &idio24gpio->reg->ttl_out0_7; in idio_24_gpio_set()
301 else if (offset > 15) in idio_24_gpio_set()
302 base = &idio24gpio->reg->out16_23; in idio_24_gpio_set()
303 else if (offset > 7) in idio_24_gpio_set()
304 base = &idio24gpio->reg->out8_15; in idio_24_gpio_set()
306 base = &idio24gpio->reg->out0_7; in idio_24_gpio_set()
308 raw_spin_lock_irqsave(&idio24gpio->lock, flags); in idio_24_gpio_set()
317 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); in idio_24_gpio_set()
324 unsigned long offset; in idio_24_gpio_set_multiple() local
327 &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15, in idio_24_gpio_set_multiple()
328 &idio24gpio->reg->out16_23 in idio_24_gpio_set_multiple()
336 for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { in idio_24_gpio_set_multiple()
337 index = offset / 8; in idio_24_gpio_set_multiple()
339 bitmask = bitmap_get_value8(bits, offset) & gpio_mask; in idio_24_gpio_set_multiple()
341 raw_spin_lock_irqsave(&idio24gpio->lock, flags); in idio_24_gpio_set_multiple()
346 } else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) { in idio_24_gpio_set_multiple()
347 out_state = ioread8(&idio24gpio->reg->ttl_out0_7); in idio_24_gpio_set_multiple()
350 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); in idio_24_gpio_set_multiple()
362 iowrite8(out_state, &idio24gpio->reg->ttl_out0_7); in idio_24_gpio_set_multiple()
364 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); in idio_24_gpio_set_multiple()
377 const unsigned long bit_offset = irqd_to_hwirq(data) - 24; in idio_24_irq_mask()
382 raw_spin_lock_irqsave(&idio24gpio->lock, flags); in idio_24_irq_mask()
384 idio24gpio->irq_mask &= ~BIT(bit_offset); in idio_24_irq_mask()
385 new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; in idio_24_irq_mask()
388 cos_enable_state = ioread8(&idio24gpio->reg->cos_enable); in idio_24_irq_mask()
395 iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable); in idio_24_irq_mask()
398 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); in idio_24_irq_mask()
407 const unsigned long bit_offset = irqd_to_hwirq(data) - 24; in idio_24_irq_unmask()
411 raw_spin_lock_irqsave(&idio24gpio->lock, flags); in idio_24_irq_unmask()
413 prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8; in idio_24_irq_unmask()
414 idio24gpio->irq_mask |= BIT(bit_offset); in idio_24_irq_unmask()
417 cos_enable_state = ioread8(&idio24gpio->reg->cos_enable); in idio_24_irq_unmask()
424 iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable); in idio_24_irq_unmask()
427 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); in idio_24_irq_unmask()
432 /* The only valid irq types are none and both-edges */ in idio_24_irq_set_type()
435 return -EINVAL; in idio_24_irq_set_type()
441 .name = "pcie-idio-24",
452 struct gpio_chip *const chip = &idio24gpio->chip; in idio_24_irq_handler()
456 raw_spin_lock(&idio24gpio->lock); in idio_24_irq_handler()
458 /* Read Change-Of-State status */ in idio_24_irq_handler()
459 irq_status = ioread32(&idio24gpio->reg->cos0_7); in idio_24_irq_handler()
461 raw_spin_unlock(&idio24gpio->lock); in idio_24_irq_handler()
468 irq_mask = idio24gpio->irq_mask & irq_status; in idio_24_irq_handler()
470 for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24) in idio_24_irq_handler()
471 generic_handle_irq(irq_find_mapping(chip->irq.domain, in idio_24_irq_handler()
474 raw_spin_lock(&idio24gpio->lock); in idio_24_irq_handler()
476 /* Clear Change-Of-State status */ in idio_24_irq_handler()
477 iowrite32(irq_status, &idio24gpio->reg->cos0_7); in idio_24_irq_handler()
479 raw_spin_unlock(&idio24gpio->lock); in idio_24_irq_handler()
497 struct device *const dev = &pdev->dev; in idio_24_probe()
507 return -ENOMEM; in idio_24_probe()
521 idio24gpio->plx = pcim_iomap_table(pdev)[pci_plx_bar_index]; in idio_24_probe()
522 idio24gpio->reg = pcim_iomap_table(pdev)[pci_bar_index]; in idio_24_probe()
524 idio24gpio->chip.label = name; in idio_24_probe()
525 idio24gpio->chip.parent = dev; in idio_24_probe()
526 idio24gpio->chip.owner = THIS_MODULE; in idio_24_probe()
527 idio24gpio->chip.base = -1; in idio_24_probe()
528 idio24gpio->chip.ngpio = IDIO_24_NGPIO; in idio_24_probe()
529 idio24gpio->chip.names = idio_24_names; in idio_24_probe()
530 idio24gpio->chip.get_direction = idio_24_gpio_get_direction; in idio_24_probe()
531 idio24gpio->chip.direction_input = idio_24_gpio_direction_input; in idio_24_probe()
532 idio24gpio->chip.direction_output = idio_24_gpio_direction_output; in idio_24_probe()
533 idio24gpio->chip.get = idio_24_gpio_get; in idio_24_probe()
534 idio24gpio->chip.get_multiple = idio_24_gpio_get_multiple; in idio_24_probe()
535 idio24gpio->chip.set = idio_24_gpio_set; in idio_24_probe()
536 idio24gpio->chip.set_multiple = idio_24_gpio_set_multiple; in idio_24_probe()
538 girq = &idio24gpio->chip.irq; in idio_24_probe()
539 girq->chip = &idio_24_irqchip; in idio_24_probe()
541 girq->parent_handler = NULL; in idio_24_probe()
542 girq->num_parents = 0; in idio_24_probe()
543 girq->parents = NULL; in idio_24_probe()
544 girq->default_type = IRQ_TYPE_NONE; in idio_24_probe()
545 girq->handler = handle_edge_irq; in idio_24_probe()
547 raw_spin_lock_init(&idio24gpio->lock); in idio_24_probe()
550 iowrite8(0, &idio24gpio->reg->soft_reset); in idio_24_probe()
556 idio24gpio->plx + PLX_PEX8311_PCI_LCS_INTCSR + 1); in idio_24_probe()
558 err = devm_gpiochip_add_data(dev, &idio24gpio->chip, idio24gpio); in idio_24_probe()
564 err = devm_request_irq(dev, pdev->irq, idio_24_irq_handler, IRQF_SHARED, in idio_24_probe()
582 .name = "pcie-idio-24",
590 MODULE_DESCRIPTION("ACCES PCIe-IDIO-24 GPIO driver");