Lines Matching +full:lock +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
47 .npins = (gend) - (gstart) + 1, \
53 raw_spinlock_t lock; member
86 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset, in gpio_reg() argument
90 u8 reg = offset / 32; in gpio_reg()
92 return priv->reg_base + reg_type_offset + reg * 4; in gpio_reg()
95 static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset) in mrfld_gpio_get() argument
97 void __iomem *gplr = gpio_reg(chip, offset, GPLR); in mrfld_gpio_get()
99 return !!(readl(gplr) & BIT(offset % 32)); in mrfld_gpio_get()
102 static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset, in mrfld_gpio_set() argument
109 raw_spin_lock_irqsave(&priv->lock, flags); in mrfld_gpio_set()
112 gpsr = gpio_reg(chip, offset, GPSR); in mrfld_gpio_set()
113 writel(BIT(offset % 32), gpsr); in mrfld_gpio_set()
115 gpcr = gpio_reg(chip, offset, GPCR); in mrfld_gpio_set()
116 writel(BIT(offset % 32), gpcr); in mrfld_gpio_set()
119 raw_spin_unlock_irqrestore(&priv->lock, flags); in mrfld_gpio_set()
123 unsigned int offset) in mrfld_gpio_direction_input() argument
126 void __iomem *gpdr = gpio_reg(chip, offset, GPDR); in mrfld_gpio_direction_input()
130 raw_spin_lock_irqsave(&priv->lock, flags); in mrfld_gpio_direction_input()
133 value &= ~BIT(offset % 32); in mrfld_gpio_direction_input()
136 raw_spin_unlock_irqrestore(&priv->lock, flags); in mrfld_gpio_direction_input()
142 unsigned int offset, int value) in mrfld_gpio_direction_output() argument
145 void __iomem *gpdr = gpio_reg(chip, offset, GPDR); in mrfld_gpio_direction_output()
148 mrfld_gpio_set(chip, offset, value); in mrfld_gpio_direction_output()
150 raw_spin_lock_irqsave(&priv->lock, flags); in mrfld_gpio_direction_output()
153 value |= BIT(offset % 32); in mrfld_gpio_direction_output()
156 raw_spin_unlock_irqrestore(&priv->lock, flags); in mrfld_gpio_direction_output()
161 static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) in mrfld_gpio_get_direction() argument
163 void __iomem *gpdr = gpio_reg(chip, offset, GPDR); in mrfld_gpio_get_direction()
165 if (readl(gpdr) & BIT(offset % 32)) in mrfld_gpio_get_direction()
171 static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, in mrfld_gpio_set_debounce() argument
175 void __iomem *gfbr = gpio_reg(chip, offset, GFBR); in mrfld_gpio_set_debounce()
179 raw_spin_lock_irqsave(&priv->lock, flags); in mrfld_gpio_set_debounce()
182 value = readl(gfbr) & ~BIT(offset % 32); in mrfld_gpio_set_debounce()
184 value = readl(gfbr) | BIT(offset % 32); in mrfld_gpio_set_debounce()
187 raw_spin_unlock_irqrestore(&priv->lock, flags); in mrfld_gpio_set_debounce()
192 static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset, in mrfld_gpio_set_config() argument
198 return -ENOTSUPP; in mrfld_gpio_set_config()
201 return mrfld_gpio_set_debounce(chip, offset, debounce); in mrfld_gpio_set_config()
208 void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR); in mrfld_irq_ack()
211 raw_spin_lock_irqsave(&priv->lock, flags); in mrfld_irq_ack()
215 raw_spin_unlock_irqrestore(&priv->lock, flags); in mrfld_irq_ack()
222 void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR); in mrfld_irq_unmask_mask()
226 raw_spin_lock_irqsave(&priv->lock, flags); in mrfld_irq_unmask_mask()
234 raw_spin_unlock_irqrestore(&priv->lock, flags); in mrfld_irq_unmask_mask()
252 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); in mrfld_irq_set_type()
253 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); in mrfld_irq_set_type()
254 void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); in mrfld_irq_set_type()
255 void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); in mrfld_irq_set_type()
259 raw_spin_lock_irqsave(&priv->lock, flags); in mrfld_irq_set_type()
295 raw_spin_unlock_irqrestore(&priv->lock, flags); in mrfld_irq_set_type()
305 void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR); in mrfld_irq_set_wake()
306 void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR); in mrfld_irq_set_wake()
310 raw_spin_lock_irqsave(&priv->lock, flags); in mrfld_irq_set_wake()
321 raw_spin_unlock_irqrestore(&priv->lock, flags); in mrfld_irq_set_wake()
323 dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio); in mrfld_irq_set_wake()
328 .name = "gpio-merrifield",
346 for (base = 0; base < priv->chip.ngpio; base += 32) { in mrfld_irq_handler()
347 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); in mrfld_irq_handler()
348 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); in mrfld_irq_handler()
360 irq = irq_find_mapping(gc->irq.domain, base + gpio); in mrfld_irq_handler()
374 for (base = 0; base < priv->chip.ngpio; base += 32) { in mrfld_irq_init_hw()
375 /* Clear the rising-edge detect register */ in mrfld_irq_init_hw()
376 reg = gpio_reg(&priv->chip, base, GRER); in mrfld_irq_init_hw()
378 /* Clear the falling-edge detect register */ in mrfld_irq_init_hw()
379 reg = gpio_reg(&priv->chip, base, GFER); in mrfld_irq_init_hw()
391 adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1); in mrfld_gpio_get_pinctrl_dev_name()
393 name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL); in mrfld_gpio_get_pinctrl_dev_name()
396 name = "pinctrl-merrifield"; in mrfld_gpio_get_pinctrl_dev_name()
413 retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name, in mrfld_gpio_add_pin_ranges()
414 range->gpio_base, in mrfld_gpio_add_pin_ranges()
415 range->pin_base, in mrfld_gpio_add_pin_ranges()
416 range->npins); in mrfld_gpio_add_pin_ranges()
418 dev_err(priv->dev, "failed to add GPIO pin range\n"); in mrfld_gpio_add_pin_ranges()
440 dev_err(&pdev->dev, "I/O memory mapping error\n"); in mrfld_gpio_probe()
452 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in mrfld_gpio_probe()
454 return -ENOMEM; in mrfld_gpio_probe()
456 priv->dev = &pdev->dev; in mrfld_gpio_probe()
457 priv->reg_base = pcim_iomap_table(pdev)[0]; in mrfld_gpio_probe()
459 priv->chip.label = dev_name(&pdev->dev); in mrfld_gpio_probe()
460 priv->chip.parent = &pdev->dev; in mrfld_gpio_probe()
461 priv->chip.request = gpiochip_generic_request; in mrfld_gpio_probe()
462 priv->chip.free = gpiochip_generic_free; in mrfld_gpio_probe()
463 priv->chip.direction_input = mrfld_gpio_direction_input; in mrfld_gpio_probe()
464 priv->chip.direction_output = mrfld_gpio_direction_output; in mrfld_gpio_probe()
465 priv->chip.get = mrfld_gpio_get; in mrfld_gpio_probe()
466 priv->chip.set = mrfld_gpio_set; in mrfld_gpio_probe()
467 priv->chip.get_direction = mrfld_gpio_get_direction; in mrfld_gpio_probe()
468 priv->chip.set_config = mrfld_gpio_set_config; in mrfld_gpio_probe()
469 priv->chip.base = gpio_base; in mrfld_gpio_probe()
470 priv->chip.ngpio = MRFLD_NGPIO; in mrfld_gpio_probe()
471 priv->chip.can_sleep = false; in mrfld_gpio_probe()
472 priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges; in mrfld_gpio_probe()
474 raw_spin_lock_init(&priv->lock); in mrfld_gpio_probe()
480 girq = &priv->chip.irq; in mrfld_gpio_probe()
481 girq->chip = &mrfld_irqchip; in mrfld_gpio_probe()
482 girq->init_hw = mrfld_irq_init_hw; in mrfld_gpio_probe()
483 girq->parent_handler = mrfld_irq_handler; in mrfld_gpio_probe()
484 girq->num_parents = 1; in mrfld_gpio_probe()
485 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, in mrfld_gpio_probe()
486 sizeof(*girq->parents), GFP_KERNEL); in mrfld_gpio_probe()
487 if (!girq->parents) in mrfld_gpio_probe()
488 return -ENOMEM; in mrfld_gpio_probe()
489 girq->parents[0] = pci_irq_vector(pdev, 0); in mrfld_gpio_probe()
490 girq->first = irq_base; in mrfld_gpio_probe()
491 girq->default_type = IRQ_TYPE_NONE; in mrfld_gpio_probe()
492 girq->handler = handle_bad_irq; in mrfld_gpio_probe()
494 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); in mrfld_gpio_probe()
496 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); in mrfld_gpio_probe()
511 .name = "gpio-merrifield",