Lines Matching +full:lock +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-DIO-48E series
6 * This driver supports the following ACCES devices: 104-DIO-48E and
7 * 104-DIO-24E.
30 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
37 * struct dio48e_gpio - GPIO device private data structure
42 * @lock: synchronization lock to prevent I/O race conditions
51 raw_spinlock_t lock; member
56 static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset) in dio48e_gpio_get_direction() argument
59 const unsigned port = offset / 8; in dio48e_gpio_get_direction()
60 const unsigned mask = BIT(offset % 8); in dio48e_gpio_get_direction()
62 if (dio48egpio->io_state[port] & mask) in dio48e_gpio_get_direction()
68 static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in dio48e_gpio_direction_input() argument
71 const unsigned io_port = offset / 8; in dio48e_gpio_direction_input()
73 const unsigned control_addr = dio48egpio->base + 3 + control_port*4; in dio48e_gpio_direction_input()
77 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_gpio_direction_input()
82 if (offset % 8 > 3) { in dio48e_gpio_direction_input()
83 dio48egpio->io_state[io_port] |= 0xF0; in dio48e_gpio_direction_input()
84 dio48egpio->control[control_port] |= BIT(3); in dio48e_gpio_direction_input()
86 dio48egpio->io_state[io_port] |= 0x0F; in dio48e_gpio_direction_input()
87 dio48egpio->control[control_port] |= BIT(0); in dio48e_gpio_direction_input()
90 dio48egpio->io_state[io_port] |= 0xFF; in dio48e_gpio_direction_input()
92 dio48egpio->control[control_port] |= BIT(4); in dio48e_gpio_direction_input()
94 dio48egpio->control[control_port] |= BIT(1); in dio48e_gpio_direction_input()
97 control = BIT(7) | dio48egpio->control[control_port]; in dio48e_gpio_direction_input()
102 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_direction_input()
107 static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in dio48e_gpio_direction_output() argument
111 const unsigned io_port = offset / 8; in dio48e_gpio_direction_output()
113 const unsigned mask = BIT(offset % 8); in dio48e_gpio_direction_output()
114 const unsigned control_addr = dio48egpio->base + 3 + control_port*4; in dio48e_gpio_direction_output()
119 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_gpio_direction_output()
124 if (offset % 8 > 3) { in dio48e_gpio_direction_output()
125 dio48egpio->io_state[io_port] &= 0x0F; in dio48e_gpio_direction_output()
126 dio48egpio->control[control_port] &= ~BIT(3); in dio48e_gpio_direction_output()
128 dio48egpio->io_state[io_port] &= 0xF0; in dio48e_gpio_direction_output()
129 dio48egpio->control[control_port] &= ~BIT(0); in dio48e_gpio_direction_output()
132 dio48egpio->io_state[io_port] &= 0x00; in dio48e_gpio_direction_output()
134 dio48egpio->control[control_port] &= ~BIT(4); in dio48e_gpio_direction_output()
136 dio48egpio->control[control_port] &= ~BIT(1); in dio48e_gpio_direction_output()
140 dio48egpio->out_state[io_port] |= mask; in dio48e_gpio_direction_output()
142 dio48egpio->out_state[io_port] &= ~mask; in dio48e_gpio_direction_output()
144 control = BIT(7) | dio48egpio->control[control_port]; in dio48e_gpio_direction_output()
147 outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port); in dio48e_gpio_direction_output()
152 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_direction_output()
157 static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset) in dio48e_gpio_get() argument
160 const unsigned port = offset / 8; in dio48e_gpio_get()
161 const unsigned mask = BIT(offset % 8); in dio48e_gpio_get()
166 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_gpio_get()
169 if (!(dio48egpio->io_state[port] & mask)) { in dio48e_gpio_get()
170 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_get()
171 return -EINVAL; in dio48e_gpio_get()
174 port_state = inb(dio48egpio->base + in_port); in dio48e_gpio_get()
176 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_get()
187 unsigned long offset; in dio48e_gpio_get_multiple() local
193 bitmap_zero(bits, chip->ngpio); in dio48e_gpio_get_multiple()
195 for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { in dio48e_gpio_get_multiple()
196 port_addr = dio48egpio->base + ports[offset / 8]; in dio48e_gpio_get_multiple()
199 bitmap_set_value8(bits, port_state, offset); in dio48e_gpio_get_multiple()
205 static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in dio48e_gpio_set() argument
208 const unsigned port = offset / 8; in dio48e_gpio_set()
209 const unsigned mask = BIT(offset % 8); in dio48e_gpio_set()
213 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_gpio_set()
216 dio48egpio->out_state[port] |= mask; in dio48e_gpio_set()
218 dio48egpio->out_state[port] &= ~mask; in dio48e_gpio_set()
220 outb(dio48egpio->out_state[port], dio48egpio->base + out_port); in dio48e_gpio_set()
222 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_set()
229 unsigned long offset; in dio48e_gpio_set_multiple() local
236 for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { in dio48e_gpio_set_multiple()
237 index = offset / 8; in dio48e_gpio_set_multiple()
238 port_addr = dio48egpio->base + ports[index]; in dio48e_gpio_set_multiple()
240 bitmask = bitmap_get_value8(bits, offset) & gpio_mask; in dio48e_gpio_set_multiple()
242 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_gpio_set_multiple()
245 dio48egpio->out_state[index] &= ~gpio_mask; in dio48e_gpio_set_multiple()
246 dio48egpio->out_state[index] |= bitmask; in dio48e_gpio_set_multiple()
247 outb(dio48egpio->out_state[index], port_addr); in dio48e_gpio_set_multiple()
249 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_gpio_set_multiple()
261 const unsigned long offset = irqd_to_hwirq(data); in dio48e_irq_mask() local
265 if (offset != 19 && offset != 43) in dio48e_irq_mask()
268 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_irq_mask()
270 if (offset == 19) in dio48e_irq_mask()
271 dio48egpio->irq_mask &= ~BIT(0); in dio48e_irq_mask()
273 dio48egpio->irq_mask &= ~BIT(1); in dio48e_irq_mask()
275 if (!dio48egpio->irq_mask) in dio48e_irq_mask()
277 inb(dio48egpio->base + 0xB); in dio48e_irq_mask()
279 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_irq_mask()
286 const unsigned long offset = irqd_to_hwirq(data); in dio48e_irq_unmask() local
290 if (offset != 19 && offset != 43) in dio48e_irq_unmask()
293 raw_spin_lock_irqsave(&dio48egpio->lock, flags); in dio48e_irq_unmask()
295 if (!dio48egpio->irq_mask) { in dio48e_irq_unmask()
297 outb(0x00, dio48egpio->base + 0xF); in dio48e_irq_unmask()
298 outb(0x00, dio48egpio->base + 0xB); in dio48e_irq_unmask()
301 if (offset == 19) in dio48e_irq_unmask()
302 dio48egpio->irq_mask |= BIT(0); in dio48e_irq_unmask()
304 dio48egpio->irq_mask |= BIT(1); in dio48e_irq_unmask()
306 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); in dio48e_irq_unmask()
311 const unsigned long offset = irqd_to_hwirq(data); in dio48e_irq_set_type() local
314 if (offset != 19 && offset != 43) in dio48e_irq_set_type()
315 return -EINVAL; in dio48e_irq_set_type()
318 return -EINVAL; in dio48e_irq_set_type()
324 .name = "104-dio-48e",
334 struct gpio_chip *const chip = &dio48egpio->chip; in dio48e_irq_handler()
335 const unsigned long irq_mask = dio48egpio->irq_mask; in dio48e_irq_handler()
339 generic_handle_irq(irq_find_mapping(chip->irq.domain, in dio48e_irq_handler()
342 raw_spin_lock(&dio48egpio->lock); in dio48e_irq_handler()
344 outb(0x00, dio48egpio->base + 0xF); in dio48e_irq_handler()
346 raw_spin_unlock(&dio48egpio->lock); in dio48e_irq_handler()
376 inb(dio48egpio->base + 0xB); in dio48e_irq_init_hw()
390 return -ENOMEM; in dio48e_probe()
393 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", in dio48e_probe()
395 return -EBUSY; in dio48e_probe()
398 dio48egpio->chip.label = name; in dio48e_probe()
399 dio48egpio->chip.parent = dev; in dio48e_probe()
400 dio48egpio->chip.owner = THIS_MODULE; in dio48e_probe()
401 dio48egpio->chip.base = -1; in dio48e_probe()
402 dio48egpio->chip.ngpio = DIO48E_NGPIO; in dio48e_probe()
403 dio48egpio->chip.names = dio48e_names; in dio48e_probe()
404 dio48egpio->chip.get_direction = dio48e_gpio_get_direction; in dio48e_probe()
405 dio48egpio->chip.direction_input = dio48e_gpio_direction_input; in dio48e_probe()
406 dio48egpio->chip.direction_output = dio48e_gpio_direction_output; in dio48e_probe()
407 dio48egpio->chip.get = dio48e_gpio_get; in dio48e_probe()
408 dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple; in dio48e_probe()
409 dio48egpio->chip.set = dio48e_gpio_set; in dio48e_probe()
410 dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple; in dio48e_probe()
411 dio48egpio->base = base[id]; in dio48e_probe()
413 girq = &dio48egpio->chip.irq; in dio48e_probe()
414 girq->chip = &dio48e_irqchip; in dio48e_probe()
416 girq->parent_handler = NULL; in dio48e_probe()
417 girq->num_parents = 0; in dio48e_probe()
418 girq->parents = NULL; in dio48e_probe()
419 girq->default_type = IRQ_TYPE_NONE; in dio48e_probe()
420 girq->handler = handle_edge_irq; in dio48e_probe()
421 girq->init_hw = dio48e_irq_init_hw; in dio48e_probe()
423 raw_spin_lock_init(&dio48egpio->lock); in dio48e_probe()
437 err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio); in dio48e_probe()
456 .name = "104-dio-48e"
462 MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");