drivers/firmware/ti_sci.h

212  *				configuration of the device
649  * @valid_params: Bitfield defining validity of ring configuration parameters.
650  *	The ring configuration fields are not valid, and will not be used for
651  *	ring configuration, if their corresponding valid bit is zero.
687  * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
689  * Gets the configuration of the non-real-time register fields of a ring.  The
705  * struct ti_sci_msg_rm_ring_get_cfg_resp -  Ring get configuration response
788  * struct ti_sci_msg_udmap_rx_flow_cfg -  UDMAP receive flow configuration
793  * @flow_index: UDMAP receive flow index for non-optional configuration.
797  * @rx_error_handling: UDMAP receive flow error handling configuration. Valid
853  *						flow optional configuration
857  * @flow_index: UDMAP receive flow index for optional configuration.
889  * in the TISCI header via the RM board configuration resource assignment
894  * @valid_params: Bitfield defining validity of tx channel configuration
895  * parameters. The tx channel configuration fields are not valid, and will not
896  * be used for ch configuration, if their corresponding valid bit is zero.
918  * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
923  * configuration to be programmed into the tx_filt_einfo field of the
927  * configuration to be programmed into the tx_filt_pswords field of the
931  * interpretation configuration to be programmed into the tx_atype field of
935  * passing mechanism configuration to be programmed into the tx_chan_type
939  * configuration to be programmed into the tx_supr_tdpkt field of the channel's
943  * fetch configuration to be programmed into the tx_fetch_size field of the
948  * configuration to be programmed into the count field of the TCHAN_TCREDIT
951  * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
954  * requesting configuration of the transmit channel.
965  * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
971  * configuration to be programmed into the priority field of the channel's
974  * @tx_burst_size: UDMAP transmit channel burst size configuration to be
1004  * in the TISCI header via the RM board configuration resource assignment
1009  * @valid_params: Bitfield defining validity of rx channel configuration
1011  * The rx channel configuration fields are not valid, and will not be used for
1012  * ch configuration, if their corresponding valid bit is zero.
1034  * fetch configuration to be programmed into the rx_fetch_size field of the
1037  * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
1040  * of the host, requesting configuration of the receive channel.
1052  * configuration to be programmed into the priority field of the channel's
1056  * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
1063  * host, requesting configuration of the receive channel.
1065  * @flowid_cnt: UDMAP receive channel additional flows count configuration to
1074  * subordinate of the host, requesting configuration of the receive channel.
1076  * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
1081  * interpretation configuration to be programmed into the rx_atype field of the
1085  * mechanism configuration to be programmed into the rx_chan_type field of the
1088  * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
1091  * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
1094  * @rx_burst_size: UDMAP receive channel burst size configuration to be
1122  * Configuration does not include the flow registers which handle size-based
1126  * the RM board configuration resource assignment range list.
1131  * Bitfield defining validity of rx flow configuration parameters.  The
1132  * rx flow configuration fields are not valid, and will not be used for flow
1133  * configuration, if their corresponding valid bit is zero.  Valid bit usage:
1157  * @flow_index: UDMAP receive flow index for non-optional configuration.
1160  * UDMAP receive flow extended packet info present configuration to be
1164  * UDMAP receive flow PS words present configuration to be programmed into the
1168  * UDMAP receive flow error handling configuration to be programmed into the
1172  * UDMAP receive flow descriptor type configuration to be programmed into the
1176  * UDMAP receive flow start of packet offset configuration to be programmed
1182  * UDMAP receive flow destination queue configuration to be programmed into the
1186  * configuration of the receive flow.
1189  * UDMAP receive flow source tag high byte constant configuration to be
1194  * UDMAP receive flow source tag low byte constant configuration to be
1199  * UDMAP receive flow destination tag high byte constant configuration to be
1204  * UDMAP receive flow destination tag low byte constant configuration to be
1209  * UDMAP receive flow source tag high byte selector configuration to be
1214  * UDMAP receive flow source tag low byte selector configuration to be
1219  * UDMAP receive flow destination tag high byte selector configuration to be
1224  * UDMAP receive flow destination tag low byte selector configuration to be
1229  * UDMAP receive flow free descriptor queue 0 configuration to be programmed
1234  * configuration of the receive flow.
1237  * UDMAP receive flow free descriptor queue 1 configuration to be programmed
1242  * configuration of the receive flow.
1245  * UDMAP receive flow free descriptor queue 2 configuration to be programmed
1250  * configuration of the receive flow.
1253  * UDMAP receive flow free descriptor queue 3 configuration to be programmed
1258  * configuration of the receive flow.
1261  * UDMAP receive flow PS words location configuration to be programmed into the
1337  * struct ti_sci_msg_req_set_config - Set Processor boot configuration