Lines Matching +full:bank +full:- +full:width
5 * Copyright (C) 2012 - 2014 Xilinx, Inc.
154 /* DDR Control Register width definitions */
270 * struct ecc_error_info - ECC error log information.
273 * @bank: Bank number.
276 * @bankgrpnr: Bank group number.
282 u32 bank; member
290 * struct synps_ecc_status - ECC status information to report.
304 * struct synps_edac_priv - DDR memory controller private instance data.
314 * @bank_shift: Bit shifts for bank bit.
315 * @bankgrp_shift: Bit shifts for bank group bit.
336 * struct synps_platform_data - synps platform data structure.
352 * zynq_get_error_info - Get the current ECC error info.
363 base = priv->baseaddr; in zynq_get_error_info()
364 p = &priv->stat; in zynq_get_error_info()
370 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; in zynq_get_error_info()
371 p->ue_cnt = regval & STAT_UECNT_MASK; in zynq_get_error_info()
374 if (!(p->ce_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
377 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; in zynq_get_error_info()
379 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
380 p->ceinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
381 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
382 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); in zynq_get_error_info()
383 edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, in zynq_get_error_info()
384 p->ceinfo.data); in zynq_get_error_info()
389 if (!(p->ue_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
393 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
394 p->ueinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
395 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
396 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); in zynq_get_error_info()
407 * zynqmp_get_error_info - Get the current ECC error info.
418 base = priv->baseaddr; in zynqmp_get_error_info()
419 p = &priv->stat; in zynqmp_get_error_info()
425 p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT; in zynqmp_get_error_info()
426 p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT; in zynqmp_get_error_info()
427 if (!p->ce_cnt) in zynqmp_get_error_info()
430 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); in zynqmp_get_error_info()
433 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
435 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
437 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
439 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
440 p->ceinfo.data = readl(base + ECC_CSYND0_OFST); in zynqmp_get_error_info()
445 if (!p->ue_cnt) in zynqmp_get_error_info()
449 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
451 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
453 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
455 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
456 p->ueinfo.data = readl(base + ECC_UESYND0_OFST); in zynqmp_get_error_info()
467 * handle_error - Handle Correctable and Uncorrectable errors.
475 struct synps_edac_priv *priv = mci->pvt_info; in handle_error()
478 if (p->ce_cnt) { in handle_error()
479 pinf = &p->ceinfo; in handle_error()
480 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
481 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
482 …"DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0… in handle_error()
483 "CE", pinf->row, pinf->bank, in handle_error()
484 pinf->bankgrpnr, pinf->blknr, in handle_error()
485 pinf->bitpos, pinf->data); in handle_error()
487 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
488 "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x", in handle_error()
489 "CE", pinf->row, pinf->bank, pinf->col, in handle_error()
490 pinf->bitpos, pinf->data); in handle_error()
494 p->ce_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
495 priv->message, ""); in handle_error()
498 if (p->ue_cnt) { in handle_error()
499 pinf = &p->ueinfo; in handle_error()
500 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
501 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
502 "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d", in handle_error()
503 "UE", pinf->row, pinf->bank, in handle_error()
504 pinf->bankgrpnr, pinf->blknr); in handle_error()
506 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
507 "DDR ECC error type :%s Row %d Bank %d Col %d ", in handle_error()
508 "UE", pinf->row, pinf->bank, pinf->col); in handle_error()
512 p->ue_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
513 priv->message, ""); in handle_error()
520 * intr_handler - Interrupt Handler for ECC interrupts.
533 priv = mci->pvt_info; in intr_handler()
534 p_data = priv->p_data; in intr_handler()
536 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
541 status = p_data->get_error_info(priv); in intr_handler()
545 priv->ce_cnt += priv->stat.ce_cnt; in intr_handler()
546 priv->ue_cnt += priv->stat.ue_cnt; in intr_handler()
547 handle_error(mci, &priv->stat); in intr_handler()
550 priv->ce_cnt, priv->ue_cnt); in intr_handler()
551 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
556 * check_errors - Check controller for ECC errors.
567 priv = mci->pvt_info; in check_errors()
568 p_data = priv->p_data; in check_errors()
570 status = p_data->get_error_info(priv); in check_errors()
574 priv->ce_cnt += priv->stat.ce_cnt; in check_errors()
575 priv->ue_cnt += priv->stat.ue_cnt; in check_errors()
576 handle_error(mci, &priv->stat); in check_errors()
579 priv->ce_cnt, priv->ue_cnt); in check_errors()
583 * zynq_get_dtype - Return the controller memory width.
586 * Get the EDAC device type width appropriate for the current controller
589 * Return: a device type width enumeration.
594 u32 width; in zynq_get_dtype() local
596 width = readl(base + CTRL_OFST); in zynq_get_dtype()
597 width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT; in zynq_get_dtype()
599 switch (width) { in zynq_get_dtype()
614 * zynqmp_get_dtype - Return the controller memory width.
617 * Get the EDAC device type width appropriate for the current controller
620 * Return: a device type width enumeration.
625 u32 width; in zynqmp_get_dtype() local
627 width = readl(base + CTRL_OFST); in zynqmp_get_dtype()
628 width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; in zynqmp_get_dtype()
629 switch (width) { in zynqmp_get_dtype()
647 * zynq_get_ecc_state - Return the controller ECC enable/disable status.
671 * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
676 * Return: a ECC status boolean i.e true/false - enabled/disabled.
696 * get_memsize - Read the size of the attached memory device.
710 * zynq_get_mtype - Return the controller memory type.
734 * zynqmp_get_mtype - Returns controller memory type.
762 * init_csrows - Initialize the csrow data.
770 struct synps_edac_priv *priv = mci->pvt_info; in init_csrows()
777 p_data = priv->p_data; in init_csrows()
779 for (row = 0; row < mci->nr_csrows; row++) { in init_csrows()
780 csi = mci->csrows[row]; in init_csrows()
783 for (j = 0; j < csi->nr_channels; j++) { in init_csrows()
784 dimm = csi->channels[j]->dimm; in init_csrows()
785 dimm->edac_mode = EDAC_FLAG_SECDED; in init_csrows()
786 dimm->mtype = p_data->get_mtype(priv->baseaddr); in init_csrows()
787 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; in init_csrows()
788 dimm->grain = SYNPS_EDAC_ERR_GRAIN; in init_csrows()
789 dimm->dtype = p_data->get_dtype(priv->baseaddr); in init_csrows()
795 * mc_init - Initialize one driver instance.
800 * related driver-private data associated with the memory controller the
807 mci->pdev = &pdev->dev; in mc_init()
808 priv = mci->pvt_info; in mc_init()
812 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; in mc_init()
813 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; in mc_init()
814 mci->scrub_cap = SCRUB_HW_SRC; in mc_init()
815 mci->scrub_mode = SCRUB_NONE; in mc_init()
817 mci->edac_cap = EDAC_FLAG_SECDED; in mc_init()
818 mci->ctl_name = "synps_ddr_controller"; in mc_init()
819 mci->dev_name = SYNPS_EDAC_MOD_STRING; in mc_init()
820 mci->mod_name = SYNPS_EDAC_MOD_VER; in mc_init()
822 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_init()
826 mci->edac_check = check_errors; in mc_init()
829 mci->ctl_page_to_phys = NULL; in mc_init()
838 priv->baseaddr + DDR_QOS_IRQ_EN_OFST); in enable_intr()
845 priv->baseaddr + DDR_QOS_IRQ_DB_OFST); in disable_intr()
851 struct synps_edac_priv *priv = mci->pvt_info; in setup_irq()
861 ret = devm_request_irq(&pdev->dev, irq, intr_handler, in setup_irq()
862 0, dev_name(&pdev->dev), mci); in setup_irq()
895 .compatible = "xlnx,zynq-ddrc-a05",
899 .compatible = "xlnx,zynqmp-ddrc-2.40a",
913 * ddr_poison_setup - Update poison registers.
921 int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval; in ddr_poison_setup() local
925 hif_addr = priv->poison_addr >> 3; in ddr_poison_setup()
928 if (priv->row_shift[index]) in ddr_poison_setup()
929 row |= (((hif_addr >> priv->row_shift[index]) & in ddr_poison_setup()
936 if (priv->col_shift[index] || index < 3) in ddr_poison_setup()
937 col |= (((hif_addr >> priv->col_shift[index]) & in ddr_poison_setup()
944 if (priv->bank_shift[index]) in ddr_poison_setup()
945 bank |= (((hif_addr >> priv->bank_shift[index]) & in ddr_poison_setup()
952 if (priv->bankgrp_shift[index]) in ddr_poison_setup()
953 bankgrp |= (((hif_addr >> priv->bankgrp_shift[index]) in ddr_poison_setup()
959 if (priv->rank_shift[0]) in ddr_poison_setup()
960 rank = (hif_addr >> priv->rank_shift[0]) & BIT(0); in ddr_poison_setup()
964 writel(regval, priv->baseaddr + ECC_POISON0_OFST); in ddr_poison_setup()
967 regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK; in ddr_poison_setup()
969 writel(regval, priv->baseaddr + ECC_POISON1_OFST); in ddr_poison_setup()
977 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_show()
981 readl(priv->baseaddr + ECC_POISON0_OFST), in inject_data_error_show()
982 readl(priv->baseaddr + ECC_POISON1_OFST), in inject_data_error_show()
983 priv->poison_addr); in inject_data_error_show()
991 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_store()
993 if (kstrtoul(data, 0, &priv->poison_addr)) in inject_data_error_store()
994 return -EINVAL; in inject_data_error_store()
1006 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_show()
1009 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3) in inject_data_poison_show()
1018 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_store()
1020 writel(0, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1022 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1024 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1025 writel(1, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1037 rc = device_create_file(&mci->dev, &dev_attr_inject_data_error); in edac_create_sysfs_attributes()
1040 rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison); in edac_create_sysfs_attributes()
1048 device_remove_file(&mci->dev, &dev_attr_inject_data_error); in edac_remove_sysfs_attributes()
1049 device_remove_file(&mci->dev, &dev_attr_inject_data_poison); in edac_remove_sysfs_attributes()
1057 priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE; in setup_row_address_map()
1058 priv->row_shift[1] = ((addrmap[5] >> 8) & in setup_row_address_map()
1064 priv->row_shift[index] = addrmap_row_b2_10 + in setup_row_address_map()
1068 priv->row_shift[2] = (addrmap[9] & in setup_row_address_map()
1070 priv->row_shift[3] = ((addrmap[9] >> 8) & in setup_row_address_map()
1072 priv->row_shift[4] = ((addrmap[9] >> 16) & in setup_row_address_map()
1074 priv->row_shift[5] = ((addrmap[9] >> 24) & in setup_row_address_map()
1076 priv->row_shift[6] = (addrmap[10] & in setup_row_address_map()
1078 priv->row_shift[7] = ((addrmap[10] >> 8) & in setup_row_address_map()
1080 priv->row_shift[8] = ((addrmap[10] >> 16) & in setup_row_address_map()
1082 priv->row_shift[9] = ((addrmap[10] >> 24) & in setup_row_address_map()
1084 priv->row_shift[10] = (addrmap[11] & in setup_row_address_map()
1088 priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1091 priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1094 priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1097 priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1100 priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1103 priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1106 priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1113 u32 width, memtype; in setup_column_address_map() local
1116 memtype = readl(priv->baseaddr + CTRL_OFST); in setup_column_address_map()
1117 width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; in setup_column_address_map()
1119 priv->col_shift[0] = 0; in setup_column_address_map()
1120 priv->col_shift[1] = 1; in setup_column_address_map()
1121 priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE; in setup_column_address_map()
1122 priv->col_shift[3] = ((addrmap[2] >> 8) & in setup_column_address_map()
1124 priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1127 priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1130 priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) == in setup_column_address_map()
1133 priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1136 priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1139 priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1142 if (width == DDRCTL_EWDTH_64) { in setup_column_address_map()
1144 priv->col_shift[10] = ((addrmap[4] & in setup_column_address_map()
1148 priv->col_shift[11] = (((addrmap[4] >> 8) & in setup_column_address_map()
1153 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1157 priv->col_shift[13] = (((addrmap[4] >> 8) & in setup_column_address_map()
1162 } else if (width == DDRCTL_EWDTH_32) { in setup_column_address_map()
1164 priv->col_shift[10] = (((addrmap[3] >> 24) & in setup_column_address_map()
1168 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1173 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1177 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1184 priv->col_shift[10] = (((addrmap[3] >> 16) & in setup_column_address_map()
1188 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1192 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1197 priv->col_shift[11] = (((addrmap[3] >> 16) & in setup_column_address_map()
1201 priv->col_shift[13] = (((addrmap[3] >> 24) & in setup_column_address_map()
1208 if (width) { in setup_column_address_map()
1209 for (index = 9; index > width; index--) { in setup_column_address_map()
1210 priv->col_shift[index] = priv->col_shift[index - width]; in setup_column_address_map()
1211 priv->col_shift[index - width] = 0; in setup_column_address_map()
1219 priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE; in setup_bank_address_map()
1220 priv->bank_shift[1] = ((addrmap[1] >> 8) & in setup_bank_address_map()
1222 priv->bank_shift[2] = (((addrmap[1] >> 16) & in setup_bank_address_map()
1231 priv->bankgrp_shift[0] = (addrmap[8] & in setup_bg_address_map()
1233 priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) == in setup_bg_address_map()
1241 priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) == in setup_rank_address_map()
1247 * setup_address_map - Set Address Map by querying ADDRMAP registers.
1263 addrmap[index] = readl(priv->baseaddr + addrmap_offset); in setup_address_map()
1279 * mc_probe - Check controller and bind driver.
1298 baseaddr = devm_ioremap_resource(&pdev->dev, res); in mc_probe()
1302 p_data = of_device_get_match_data(&pdev->dev); in mc_probe()
1304 return -ENODEV; in mc_probe()
1306 if (!p_data->get_ecc_state(baseaddr)) { in mc_probe()
1308 return -ENXIO; in mc_probe()
1323 return -ENOMEM; in mc_probe()
1326 priv = mci->pvt_info; in mc_probe()
1327 priv->baseaddr = baseaddr; in mc_probe()
1328 priv->p_data = p_data; in mc_probe()
1332 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_probe()
1346 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) { in mc_probe()
1354 if (of_device_is_compatible(pdev->dev.of_node, in mc_probe()
1355 "xlnx,zynqmp-ddrc-2.40a")) in mc_probe()
1363 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)) in mc_probe()
1375 * mc_remove - Unbind driver from controller.
1383 struct synps_edac_priv *priv = mci->pvt_info; in mc_remove()
1385 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_remove()
1389 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) in mc_remove()
1393 edac_mc_del_mc(&pdev->dev); in mc_remove()
1401 .name = "synopsys-edac",