Lines Matching +full:memory +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0-only
24 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
27 * As realized in the 405EX[r], this controller features:
29 * - Support for registered- and non-registered DDR1 and DDR2 memory.
30 * - 32-bit or 16-bit memory interface with optional ECC.
34 * - 4-bit SEC/DED
35 * - Aligned-nibble error detect
36 * - Bypass mode
38 * - Two (2) memory banks/ranks.
39 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
40 * bank/rank in 16-bit mode.
42 * As realized in the 440SP and 440SPe, this controller changes/adds:
44 * - 64-bit or 32-bit memory interface with optional ECC.
48 * - 8-bit SEC/DED
49 * - Aligned-nibble error detect
50 * - Bypass mode
52 * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
53 * per bank/rank in 32-bit mode.
55 * As realized in the 460EX and 460GT, this controller changes/adds:
57 * - 64-bit or 32-bit memory interface with optional ECC.
61 * - 8-bit SEC/DED
62 * - Aligned-nibble error detect
63 * - Bypass mode
65 * - Four (4) memory banks/ranks.
66 * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
67 * per bank/rank in 32-bit mode.
69 * At present, this driver has ONLY been tested against the controller
71 * boards (256 MiB w/o ECC memory soldered onto the board) and a
72 * proprietary board based on those designs (128 MiB ECC memory, also
76 * other realizations of this controller listed above.
79 * realizations of this controller as well as broken apart to handle
80 * the other known ECC-capable controllers prevalent in other 4xx
83 * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
84 * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
85 * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
87 * For this controller, unfortunately, correctable errors report
95 * following pieces of information in the driver-unique message to the
98 * - Device tree path
99 * - Bank(s)
100 * - Check bit error group
101 * - Beat(s)/lane(s)
135 << (20 - PAGE_SHIFT + \
139 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
152 #define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */
153 #define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */
158 * PPC4xx SDRAM memory controller private instance data
163 int sec; /* Single-bit correctable error IRQ assigned */
164 int ded; /* Double-bit detectable error IRQ assigned */
193 .compatible = "ibm,sdram-4xx-ddr2"
210 * set based on the aforementioned variant controller realizations.
221 [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0",
222 [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1",
232 * mfsdram - read and return controller register data
237 * controller's specified indirect DCR register.
244 return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, in mfsdram()
245 dcr_host->base + SDRAM_DCR_DATA_OFFSET, in mfsdram()
250 * mtsdram - write controller register data
255 * This routine writes the provided data to the controller's specified
261 return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET, in mtsdram()
262 dcr_host->base + SDRAM_DCR_DATA_OFFSET, in mtsdram()
268 * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error
285 return status->ecces & SDRAM_ECCES_BK0ER; in ppc4xx_edac_check_bank_error()
287 return status->ecces & SDRAM_ECCES_BK1ER; in ppc4xx_edac_check_bank_error()
294 * ppc4xx_edac_generate_bank_message - generate interpretted bank status message
295 * @mci: A pointer to the EDAC memory controller instance associated
304 * driver-unique report message associated with the ECCESS[BKNER]
319 n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name); in ppc4xx_edac_generate_bank_message()
325 size -= n; in ppc4xx_edac_generate_bank_message()
328 for (rows = 0, row = 0; row < mci->nr_csrows; row++) { in ppc4xx_edac_generate_bank_message()
337 size -= n; in ppc4xx_edac_generate_bank_message()
348 size -= n; in ppc4xx_edac_generate_bank_message()
356 * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message
357 * @mci: A pointer to the EDAC memory controller instance associated
366 * driver-unique report message associated with the ECCESS[CKBER]
378 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_edac_generate_checkbit_message()
381 switch (status->ecces & SDRAM_ECCES_CKBER_MASK) { in ppc4xx_edac_generate_checkbit_message()
389 switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) & in ppc4xx_edac_generate_checkbit_message()
414 * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
415 * @mci: A pointer to the EDAC memory controller instance associated
424 * driver-unique report message associated with the ECCESS[BNCE]
447 size -= n; in ppc4xx_edac_generate_lane_message()
451 if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) { in ppc4xx_edac_generate_lane_message()
460 size -= n; in ppc4xx_edac_generate_lane_message()
471 size -= n; in ppc4xx_edac_generate_lane_message()
479 * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message
480 * @mci: A pointer to the EDAC memory controller instance associated
489 * driver-unique report message associated with the ECCESS register of
509 size -= n; in ppc4xx_edac_generate_ecc_message()
518 size -= n; in ppc4xx_edac_generate_ecc_message()
527 size -= n; in ppc4xx_edac_generate_ecc_message()
535 * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message
536 * @mci: A pointer to the EDAC memory controller instance associated
545 * driver-unique report message associated with the PLB-related BESR
560 if ((status->besr & SDRAM_BESR_MASK) == 0) in ppc4xx_edac_generate_plb_message()
563 if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE) in ppc4xx_edac_generate_plb_message()
566 read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ); in ppc4xx_edac_generate_plb_message()
568 master = SDRAM_BESR_M0ID_DECODE(status->besr); in ppc4xx_edac_generate_plb_message()
580 * ppc4xx_edac_generate_message - generate interpretted status message
581 * @mci: A pointer to the EDAC memory controller instance associated
582 * with the driver-unique message being generated.
589 * This routine generates to the provided buffer the driver-unique
609 size -= n; in ppc4xx_edac_generate_message()
616 * ppc4xx_ecc_dump_status - dump controller ECC status registers
617 * @mci: A pointer to the EDAC memory controller instance
640 status->ecces, in ppc4xx_ecc_dump_status()
641 status->wmirq, in ppc4xx_ecc_dump_status()
642 status->besr, in ppc4xx_ecc_dump_status()
643 status->bearh, in ppc4xx_ecc_dump_status()
644 status->bearl, in ppc4xx_ecc_dump_status()
650 * ppc4xx_ecc_get_status - get controller ECC status
651 * @mci: A pointer to the EDAC memory controller instance
657 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
666 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_ecc_get_status()
667 const dcr_host_t *dcr_host = &pdata->dcr_host; in ppc4xx_ecc_get_status()
669 status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK; in ppc4xx_ecc_get_status()
670 status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK; in ppc4xx_ecc_get_status()
671 status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK; in ppc4xx_ecc_get_status()
672 status->bearl = mfsdram(dcr_host, SDRAM_BEARL); in ppc4xx_ecc_get_status()
673 status->bearh = mfsdram(dcr_host, SDRAM_BEARH); in ppc4xx_ecc_get_status()
677 * ppc4xx_ecc_clear_status - clear controller ECC status
678 * @mci: A pointer to the EDAC memory controller instance
683 * This routine clears--by writing the masked (as appropriate) status
684 * values back to--the status registers that deal with
685 * ibm,sdram-4xx-ddr2 ECC errors.
691 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_ecc_clear_status()
692 const dcr_host_t *dcr_host = &pdata->dcr_host; in ppc4xx_ecc_clear_status()
694 mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK); in ppc4xx_ecc_clear_status()
695 mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK); in ppc4xx_ecc_clear_status()
696 mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK); in ppc4xx_ecc_clear_status()
702 * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE)
703 * @mci: A pointer to the EDAC memory controller instance
708 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
711 * interface, so we just pass driver-unique message to the "no info"
723 for (row = 0; row < mci->nr_csrows; row++) in ppc4xx_edac_handle_ce()
727 row, 0, -1, in ppc4xx_edac_handle_ce()
732 * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE)
733 * @mci: A pointer to the EDAC memory controller instance
739 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
746 const u64 bear = ((u64)status->bearh << 32 | status->bearl); in ppc4xx_edac_handle_ue()
754 for (row = 0; row < mci->nr_csrows; row++) in ppc4xx_edac_handle_ue()
758 row, 0, -1, in ppc4xx_edac_handle_ue()
763 * ppc4xx_edac_check - check controller for ECC errors
764 * @mci: A pointer to the EDAC memory controller instance
765 * associated with the ibm,sdram-4xx-ddr2 controller being
797 * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine
799 * @dev_id: A pointer to the EDAC memory controller instance
803 * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
804 * controller. It simply calls through to the same routine used during
820 * ppc4xx_edac_get_dtype - return the controller memory width
821 * @mcopt1: The 32-bit Memory Controller Option 1 register value
822 * currently set for the controller, from which the width
826 * current controller configuration.
829 * flags or some such when other controller variants are supported as
830 * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
831 * 16- and 64-bit field definition/value/enumeration (b1) overloaded
849 * ppc4xx_edac_get_mtype - return controller memory type
850 * @mcopt1: The 32-bit Memory Controller Option 1 register value
851 * currently set for the controller, from which the memory type
854 * This routine returns the EDAC memory type appropriate for the
855 * current controller configuration.
857 * Returns a memory type enumeration.
874 * ppc4xx_edac_init_csrows - initialize driver instance rows
875 * @mci: A pointer to the EDAC memory controller instance
876 * associated with the ibm,sdram-4xx-ddr2 controller for which
878 * @mcopt1: The 32-bit Memory Controller Option 1 register value
879 * currently set for the controller, from which bank width
880 * and memory typ information is derived.
883 * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
884 * controller bank/rank is mapped to a row.
886 * Returns 0 if OK; otherwise, -EINVAL if the memory bank size
891 const struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_edac_init_csrows()
899 /* Establish the memory type and width */ in ppc4xx_edac_init_csrows()
906 if (mci->edac_cap & EDAC_FLAG_SECDED) in ppc4xx_edac_init_csrows()
908 else if (mci->edac_cap & EDAC_FLAG_EC) in ppc4xx_edac_init_csrows()
915 * 1:1 with a controller bank/rank. in ppc4xx_edac_init_csrows()
918 for (row = 0; row < mci->nr_csrows; row++) { in ppc4xx_edac_init_csrows()
919 struct csrow_info *csi = mci->csrows[row]; in ppc4xx_edac_init_csrows()
926 mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row)); in ppc4xx_edac_init_csrows()
952 "Unrecognized memory bank %d " in ppc4xx_edac_init_csrows()
955 status = -EINVAL; in ppc4xx_edac_init_csrows()
969 * page size (PAGE_SIZE) or the memory width (2 or 4). in ppc4xx_edac_init_csrows()
971 for (j = 0; j < csi->nr_channels; j++) { in ppc4xx_edac_init_csrows()
972 struct dimm_info *dimm = csi->channels[j]->dimm; in ppc4xx_edac_init_csrows()
974 dimm->nr_pages = nr_pages / csi->nr_channels; in ppc4xx_edac_init_csrows()
975 dimm->grain = 1; in ppc4xx_edac_init_csrows()
977 dimm->mtype = mtype; in ppc4xx_edac_init_csrows()
978 dimm->dtype = dtype; in ppc4xx_edac_init_csrows()
980 dimm->edac_mode = edac_mode; in ppc4xx_edac_init_csrows()
989 * ppc4xx_edac_mc_init - initialize driver instance
990 * @mci: A pointer to the EDAC memory controller instance being
993 * with the controller this EDAC instance is bound to.
995 * for this controller instance.
996 * @mcopt1: The 32-bit Memory Controller Option 1 register value
997 * currently set for the controller, from which ECC capabilities
1000 * This routine performs initialization of the EDAC memory controller
1001 * instance and related driver-private data associated with the
1002 * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
1013 const struct device_node *np = op->dev.of_node; in ppc4xx_edac_mc_init()
1015 if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL) in ppc4xx_edac_mc_init()
1016 return -EINVAL; in ppc4xx_edac_mc_init()
1020 mci->pdev = &op->dev; in ppc4xx_edac_mc_init()
1022 dev_set_drvdata(mci->pdev, mci); in ppc4xx_edac_mc_init()
1024 pdata = mci->pvt_info; in ppc4xx_edac_mc_init()
1026 pdata->dcr_host = *dcr_host; in ppc4xx_edac_mc_init()
1028 /* Initialize controller capabilities and configuration */ in ppc4xx_edac_mc_init()
1030 mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR | in ppc4xx_edac_mc_init()
1033 mci->edac_ctl_cap = (EDAC_FLAG_NONE | in ppc4xx_edac_mc_init()
1037 mci->scrub_cap = SCRUB_NONE; in ppc4xx_edac_mc_init()
1038 mci->scrub_mode = SCRUB_NONE; in ppc4xx_edac_mc_init()
1047 mci->edac_cap = EDAC_FLAG_EC; in ppc4xx_edac_mc_init()
1050 mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED); in ppc4xx_edac_mc_init()
1051 mci->scrub_mode = SCRUB_SW_SRC; in ppc4xx_edac_mc_init()
1054 mci->edac_cap = EDAC_FLAG_NONE; in ppc4xx_edac_mc_init()
1060 mci->mod_name = PPC4XX_EDAC_MODULE_NAME; in ppc4xx_edac_mc_init()
1061 mci->ctl_name = ppc4xx_edac_match->compatible, in ppc4xx_edac_mc_init()
1062 mci->dev_name = np->full_name; in ppc4xx_edac_mc_init()
1066 mci->edac_check = ppc4xx_edac_check; in ppc4xx_edac_mc_init()
1067 mci->ctl_page_to_phys = NULL; in ppc4xx_edac_mc_init()
1081 * ppc4xx_edac_register_irq - setup and register controller interrupts
1083 * with the controller this EDAC instance is bound to.
1084 * @mci: A pointer to the EDAC memory controller instance
1085 * associated with the ibm,sdram-4xx-ddr2 controller for which
1090 * the associated EDAC memory controller instance.
1092 * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be
1100 struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_edac_register_irq()
1101 struct device_node *np = op->dev.of_node; in ppc4xx_edac_register_irq()
1109 status = -ENODEV; in ppc4xx_edac_register_irq()
1123 status = -ENODEV; in ppc4xx_edac_register_irq()
1137 status = -ENODEV; in ppc4xx_edac_register_irq()
1144 pdata->irqs.ded = ded_irq; in ppc4xx_edac_register_irq()
1145 pdata->irqs.sec = sec_irq; in ppc4xx_edac_register_irq()
1160 * ppc4xx_edac_map_dcrs - locate and map controller registers
1167 * register resources associated with the controller's indirect DCR
1179 return -EINVAL; in ppc4xx_edac_map_dcrs()
1189 return -ENODEV; in ppc4xx_edac_map_dcrs()
1196 return -ENODEV; in ppc4xx_edac_map_dcrs()
1205 return -ENODEV; in ppc4xx_edac_map_dcrs()
1212 * ppc4xx_edac_probe - check controller and bind driver
1214 * with the controller being probed for driver binding.
1216 * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1219 * Returns 0 if the controller instance was successfully bound to the
1227 const struct device_node *np = op->dev.of_node; in ppc4xx_edac_probe()
1233 * At this point, we only support the controller realized on in ppc4xx_edac_probe()
1237 if (!of_device_is_compatible(np, "ibm,sdram-405ex") && in ppc4xx_edac_probe()
1238 !of_device_is_compatible(np, "ibm,sdram-405exr")) { in ppc4xx_edac_probe()
1241 return -ENODEV; in ppc4xx_edac_probe()
1246 * can probe the controller. in ppc4xx_edac_probe()
1257 * for this controller. in ppc4xx_edac_probe()
1264 ppc4xx_edac_printk(KERN_INFO, "%pOF: No ECC memory detected or " in ppc4xx_edac_probe()
1266 status = -ENODEV; in ppc4xx_edac_probe()
1272 * controller instance and perform the appropriate in ppc4xx_edac_probe()
1287 status = -ENOMEM; in ppc4xx_edac_probe()
1301 * controller. Attempt to register it with the EDAC subsystem in ppc4xx_edac_probe()
1308 status = -ENODEV; in ppc4xx_edac_probe()
1324 edac_mc_del_mc(mci->pdev); in ppc4xx_edac_probe()
1334 * ppc4xx_edac_remove - unbind driver from controller
1336 * with the controller this EDAC instance is to be unbound/removed
1339 * This routine unbinds the EDAC memory controller instance associated
1340 * with the specified ibm,sdram-4xx-ddr2 controller described by the
1348 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); in ppc4xx_edac_remove()
1349 struct ppc4xx_edac_pdata *pdata = mci->pvt_info; in ppc4xx_edac_remove()
1352 free_irq(pdata->irqs.sec, mci); in ppc4xx_edac_remove()
1353 free_irq(pdata->irqs.ded, mci); in ppc4xx_edac_remove()
1356 dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN); in ppc4xx_edac_remove()
1358 edac_mc_del_mc(mci->pdev); in ppc4xx_edac_remove()
1365 * ppc4xx_edac_opstate_init - initialize EDAC reporting method
1367 * This routine ensures that the EDAC memory controller reporting
1394 * ppc4xx_edac_init - driver/module insertion entry point
1397 * initializes the EDAC memory controller reporting state and
1412 * ppc4xx_edac_exit - driver/module removal entry point
1429 MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");