1 // SPDX-License-Identifier: GPL-2.0
9 	struct amd64_pvt *pvt = mci->pvt_info;  in amd64_inject_section_show()
10 	return sprintf(buf, "0x%x\n", pvt->injection.section);  in amd64_inject_section_show()
14  * store error injection section value which refers to one of 4 16-byte sections
15  * within a 64-byte cacheline
24 	struct amd64_pvt *pvt = mci->pvt_info;  in amd64_inject_section_store()
33 		amd64_warn("%s: invalid section 0x%lx\n", __func__, value);  in amd64_inject_section_store()
34 		return -EINVAL;  in amd64_inject_section_store()
37 	pvt->injection.section = (u32) value;  in amd64_inject_section_store()
46 	struct amd64_pvt *pvt = mci->pvt_info;  in amd64_inject_word_show()
47 	return sprintf(buf, "0x%x\n", pvt->injection.word);  in amd64_inject_word_show()
51  * store error injection word value which refers to one of 9 16-bit word of the
52  * 16-byte (128-bit + ECC bits) section
61 	struct amd64_pvt *pvt = mci->pvt_info;  in amd64_inject_word_store()
71 		return -EINVAL;  in amd64_inject_word_store()
74 	pvt->injection.word = (u32) value;  in amd64_inject_word_store()
83 	struct amd64_pvt *pvt = mci->pvt_info;  in amd64_inject_ecc_vector_show()
84 	return sprintf(buf, "0x%x\n", pvt->injection.bit_map);  in amd64_inject_ecc_vector_show()
97 	struct amd64_pvt *pvt = mci->pvt_info;  in amd64_inject_ecc_vector_store()
107 		return -EINVAL;  in amd64_inject_ecc_vector_store()
110 	pvt->injection.bit_map = (u32) value;  in amd64_inject_ecc_vector_store()
123 	struct amd64_pvt *pvt = mci->pvt_info;  in amd64_inject_read_store()
125 	u32 section, word_bits;  in amd64_inject_read_store()  local
132 	/* Form value to choose 16-byte section of cacheline */  in amd64_inject_read_store()
133 	section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);  in amd64_inject_read_store()
135 	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);  in amd64_inject_read_store()
137 	word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection);  in amd64_inject_read_store()
140 	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);  in amd64_inject_read_store()
142 	edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);  in amd64_inject_read_store()
156 	struct amd64_pvt *pvt = mci->pvt_info;  in amd64_inject_write_store()
157 	u32 section, word_bits, tmp;  in amd64_inject_write_store()  local
165 	/* Form value to choose 16-byte section of cacheline */  in amd64_inject_write_store()
166 	section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);  in amd64_inject_write_store()
168 	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);  in amd64_inject_write_store()
170 	word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection);  in amd64_inject_write_store()
179 	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);  in amd64_inject_write_store()
183 	amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);  in amd64_inject_write_store()
191 	edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);  in amd64_inject_write_store()
225 	struct amd64_pvt *pvt = mci->pvt_info;  in amd64_edac_inj_is_visible()
227 	if (pvt->fam < 0x10)  in amd64_edac_inj_is_visible()
229 	return attr->mode;  in amd64_edac_inj_is_visible()