Lines Matching full:dram
56 * is within a range affected by memory hoisting. The DRAM Base
57 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
60 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
83 * The memory controller for a given node uses its DRAM CS Base and
84 * DRAM CS Mask registers to map an InputAddr to a csrow. See
169 * Function 2 - DRAM controller
317 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
339 u32 ecc_ctrl; /* DRAM ECC Control reg */
358 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
359 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
360 u32 dchr0; /* DRAM Configuration High DCT0 reg */
361 u32 dchr1; /* DRAM Configuration High DCT1 reg */
365 u32 dhar; /* DRAM Hoist reg */
366 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
367 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
372 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
378 u32 dct_sel_lo; /* DRAM Controller Select Low */
379 u32 dct_sel_hi; /* DRAM Controller Select High */