drivers/edac/amd64_edac.h

343 struct amd64_pvt {  struct
344 	struct low_ops *ops;
347 	struct pci_dev *F0, *F1, *F2, *F3, *F6;
349 	u16 mc_node_id;		/* MC index of this MC node */
350 	u8 fam;			/* CPU family */
351 	u8 model;		/* ... model */
352 	u8 stepping;		/* ... stepping */
354 	int ext_model;		/* extended model value of this node */
355 	int channel_count;
358 	u32 dclr0;		/* DRAM Configuration Low DCT0 reg */
359 	u32 dclr1;		/* DRAM Configuration Low DCT1 reg */
360 	u32 dchr0;		/* DRAM Configuration High DCT0 reg */
361 	u32 dchr1;		/* DRAM Configuration High DCT1 reg */
362 	u32 nbcap;		/* North Bridge Capabilities */
363 	u32 nbcfg;		/* F10 North Bridge Configuration */
364 	u32 ext_nbcfg;		/* Extended F10 North Bridge Configuration */
365 	u32 dhar;		/* DRAM Hoist reg */
366 	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
367 	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */
370 	struct chip_select csels[NUM_CONTROLLERS];
373 	struct dram_range ranges[DRAM_RANGES];
375 	u64 top_mem;		/* top of memory below 4GB */
376 	u64 top_mem2;		/* top of memory above 4GB */
378 	u32 dct_sel_lo;		/* DRAM Controller Select Low */
379 	u32 dct_sel_hi;		/* DRAM Controller Select High */
380 	u32 online_spare;	/* On-Line spare Reg */
383 	u8 ecc_sym_sz;
386 	struct error_injection injection;
389 	enum mem_type dram_type;
391 	struct amd64_umc *umc;	/* UMC registers */