Lines Matching +full:memory +full:- +full:controller

16 	  EDAC is a subsystem along with hardware-specific drivers designed to
17 	  report hardware errors. These are low-level errors that are reported
19 	  memory errors, cache errors, PCI errors, thermal throttling, etc..
22 	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 	  levels are 0-4 (from low to high) and by default it is set to 2.
44 	tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 	  occurring on your machine in human-readable form.
59 	  Not all machines support hardware-driven error report. Some of those
60 	  provide a BIOS-driven error report mechanism via ACPI, using the
64 	  When this option is enabled, it will disable the hardware-driven
68 	  It should be noticed that keeping both GHES and a hardware-driven
82 	  the AMD64 families (>= K8) of memory controllers.
88 	  Recent Opterons (Family 10h and later) provide for Memory Error
93 	  When enabled, in each of the respective memory controller directories
96 	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 	  - inject_word (0..8, 16-bit word of 16-byte section),
98 	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
104 	tristate "Amazon's Annapurna Lab Memory Controller"
137 	  82443BX/GX memory controllers (440BX/GX chipsets).
172 	  E3-1200 based DRAM controllers.
193 	  i7 Core (Nehalem) Integrated Memory Controller that exists on
233 	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
237 	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
247 	  Skylake server Integrated Memory Controllers. If your
248 	  system has non-volatile DIMMs you should also manually
259 	  10nm server Integrated Memory Controllers. If your
260 	  system has non-volatile DIMMs you should also manually
268 	  Pondicherry2 Integrated Memory Controller. This SoC IP is
270 	  micro-server but may appear on others in the future.
283 	  Support for error detection and correction on Freescale memory
301 	tristate "Cell Broadband Engine memory controller"
305 	  Cell Broadband Engine internal memory controller
309 	tristate "PPC4xx IBM DDR2 Memory Controller"
312 	  This enables support for EDAC on the ECC memory used
313 	  with the IBM DDR2 memory controller found in various
318 	tristate "AMD8131 HyperTransport PCI-X Tunnel"
322 	  AMD8131 HyperTransport PCI-X Tunnel chip.
336 	tristate "IBM CPC925 Memory Controller (PPC970FX)"
340 	  IBM CPC925 Bridge and Memory Controller, which is
345 	tristate "Highbank Memory Controller"
349 	  Calxeda Highbank memory controller.
356 	  Calxeda Highbank memory controller.
373 	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
380 	tristate "Cavium Octeon PCI Controller"
392 	  Cavium ThunderX memory controllers (LMC), Cache
409 	  Altera SDRAM Memory for Altera SoCs. Note that the
418 	  Altera L2 cache Memory for Altera SoCs. This option
422 	bool "Altera On-Chip RAM ECC"
426 	  Altera On-Chip RAM Memory for Altera SoCs.
433 	  Altera Ethernet FIFO Memory for Altera SoCs.
440 	  Altera NAND FIFO Memory for Altera SoCs.
447 	  Altera DMA FIFO Memory for Altera SoCs.
454 	  Altera USB FIFO Memory for Altera SoCs.
461 	  Altera QSPI FIFO Memory for Altera SoCs.
468 	  Altera SDMMC FIFO Memory for Altera SoCs.
484 	tristate "Synopsys DDR Memory Controller"
488 	  memory controller.
491 	tristate "APM X-Gene SoC"
495 	  APM X-Gene family of SOCs.
498 	tristate "Texas Instruments DDR3 ECC Controller"
504 	tristate "QCOM EDAC Controller"
511 	  As of now, it supports error reporting for Last Level Cache Controller (LLCC)
527 	tristate "Mellanox BlueField Memory ECC"
534 	tristate "ARM DMC-520 ECC"
538 	  SoCs with ARM DMC-520 DRAM controller.