Lines Matching +full:0 +full:x10001
33 #define SIRFSOC_DMA_CH_ADDR 0x00
34 #define SIRFSOC_DMA_CH_XLEN 0x04
35 #define SIRFSOC_DMA_CH_YLEN 0x08
36 #define SIRFSOC_DMA_CH_CTRL 0x0C
38 #define SIRFSOC_DMA_WIDTH_0 0x100
39 #define SIRFSOC_DMA_CH_VALID 0x140
40 #define SIRFSOC_DMA_CH_INT 0x144
41 #define SIRFSOC_DMA_INT_EN 0x148
42 #define SIRFSOC_DMA_INT_EN_CLR 0x14C
43 #define SIRFSOC_DMA_CH_LOOP_CTRL 0x150
44 #define SIRFSOC_DMA_CH_LOOP_CTRL_CLR 0x154
45 #define SIRFSOC_DMA_WIDTH_ATLAS7 0x10
46 #define SIRFSOC_DMA_VALID_ATLAS7 0x14
47 #define SIRFSOC_DMA_INT_ATLAS7 0x18
48 #define SIRFSOC_DMA_INT_EN_ATLAS7 0x1c
49 #define SIRFSOC_DMA_LOOP_CTRL_ATLAS7 0x20
50 #define SIRFSOC_DMA_CUR_DATA_ADDR 0x34
51 #define SIRFSOC_DMA_MUL_ATLAS7 0x38
52 #define SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7 0x158
53 #define SIRFSOC_DMA_CH_LOOP_CTRL_CLR_ATLAS7 0x15C
54 #define SIRFSOC_DMA_IOBG_SCMD_EN 0x800
55 #define SIRFSOC_DMA_EARLY_RESP_SET 0x818
56 #define SIRFSOC_DMA_EARLY_RESP_CLR 0x81C
68 #define SIRFSOC_DMA_INT_FINI_INT_ATLAS7 BIT(0)
74 #define SIRFSOC_DMA_INT_ALL_ATLAS7 0x3F
78 #define SIRFSOC_DMA_XLEN_MAX_V1 0x800
79 #define SIRFSOC_DMA_XLEN_MAX_V2 0x1000
138 SIRFSOC_DMA_CHAIN_NORMAL = 0x01,
139 SIRFSOC_DMA_CHAIN_PAUSE = 0x02,
140 SIRFSOC_DMA_CHAIN_LOOP = 0x03,
141 SIRFSOC_DMA_CHAIN_END = 0x04
170 (0x8 << SIRFSOC_DMA_TAB_NUM_ATLAS7) | 0x3, in sirfsoc_dma_execute_hw_a7v2()
182 0x3, base + SIRFSOC_DMA_CH_CTRL); in sirfsoc_dma_execute_hw_a7v2()
190 writel(0x10001, base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); in sirfsoc_dma_execute_hw_a7v2()
201 base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL); in sirfsoc_dma_execute_hw_a7v1()
202 writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN); in sirfsoc_dma_execute_hw_a7v1()
203 writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN); in sirfsoc_dma_execute_hw_a7v1()
206 writel(sdesc->addr >> 2, base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR); in sirfsoc_dma_execute_hw_a7v1()
221 base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL); in sirfsoc_dma_execute_hw_a6()
222 writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN); in sirfsoc_dma_execute_hw_a6()
223 writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN); in sirfsoc_dma_execute_hw_a6()
226 writel(sdesc->addr >> 2, base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR); in sirfsoc_dma_execute_hw_a6()
254 cid = 0; in sirfsoc_dma_execute()
260 schan->happened_cyclic = schan->completed_cyclic = 0; in sirfsoc_dma_execute()
279 while ((ch = fls(is) - 1) >= 0) { in sirfsoc_dma_irq()
304 schan = &sdma->channels[0]; in sirfsoc_dma_irq()
340 dma_cookie_t last_cookie = 0; in sirfsoc_dma_process_completed()
349 for (i = 0; i < sdma->dma.chancnt; i++) { in sirfsoc_dma_process_completed()
436 schan->mode = (config->src_maxburst == 4 ? 1 : 0); in sirfsoc_dma_slave_config()
439 return 0; in sirfsoc_dma_slave_config()
461 writel_relaxed(0, sdma->base + SIRFSOC_DMA_INT_EN_ATLAS7); in sirfsoc_dma_terminate_all()
464 writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); in sirfsoc_dma_terminate_all()
465 writel_relaxed(0, sdma->base + SIRFSOC_DMA_VALID_ATLAS7); in sirfsoc_dma_terminate_all()
485 return 0; in sirfsoc_dma_terminate_all()
504 writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7); in sirfsoc_dma_pause_chan()
519 return 0; in sirfsoc_dma_pause_chan()
536 writel_relaxed(0x10001, in sirfsoc_dma_resume_chan()
552 return 0; in sirfsoc_dma_resume_chan()
568 for (i = 0; i < SIRFSOC_DMA_DESCRIPTORS; i++) { in sirfsoc_dma_alloc_chan_resources()
584 if (i == 0) in sirfsoc_dma_alloc_chan_resources()
657 dma_set_residue(txstate, 0); in sirfsoc_dma_tx_status()
671 cid = 0; in sirfsoc_dma_tx_status()
677 sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR) << 2; in sirfsoc_dma_tx_status()
715 ret = 0; in sirfsoc_dma_prep_interleaved()
724 * and ylen (number of frame - 1) must be at least 0 in sirfsoc_dma_prep_interleaved()
726 if ((xt->frame_size == 1) && (xt->numf > 0)) { in sirfsoc_dma_prep_interleaved()
727 sdesc->cyclic = 0; in sirfsoc_dma_prep_interleaved()
728 sdesc->xlen = xt->sgl[0].size / SIRFSOC_DMA_WORD_LEN; in sirfsoc_dma_prep_interleaved()
729 sdesc->width = (xt->sgl[0].size + xt->sgl[0].icg) / in sirfsoc_dma_prep_interleaved()
737 sdesc->dir = 0; in sirfsoc_dma_prep_interleaved()
767 * If the X-length is set to 0, it would be the loop mode. in sirfsoc_dma_prep_cyclic()
795 sdesc->xlen = 0; in sirfsoc_dma_prep_cyclic()
831 unsigned int request = dma_spec->args[0]; in of_dma_sirfsoc_xlate()
867 sdma->irq = irq_of_parse_and_map(dn, 0); in sirfsoc_dma_probe()
879 ret = of_address_to_resource(dn, 0, &res); in sirfsoc_dma_probe()
895 ret = request_irq(sdma->irq, &sirfsoc_dma_irq, 0, DRV_NAME, sdma); in sirfsoc_dma_probe()
925 for (i = 0; i < SIRFSOC_DMA_CHANNELS; i++) { in sirfsoc_dma_probe()
960 return 0; in sirfsoc_dma_probe()
985 return 0; in sirfsoc_dma_remove()
993 return 0; in sirfsoc_dma_runtime_suspend()
1002 if (ret < 0) { in sirfsoc_dma_runtime_resume()
1006 return 0; in sirfsoc_dma_runtime_resume()
1025 if (ret < 0) in sirfsoc_dma_pm_suspend()
1041 for (ch = 0; ch < count; ch++) { in sirfsoc_dma_pm_suspend()
1046 ch * 0x10 + SIRFSOC_DMA_CH_CTRL); in sirfsoc_dma_pm_suspend()
1053 return 0; in sirfsoc_dma_pm_suspend()
1070 if (ret < 0) in sirfsoc_dma_pm_resume()
1084 for (ch = 0; ch < count; ch++) { in sirfsoc_dma_pm_resume()
1094 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_XLEN); in sirfsoc_dma_pm_resume()
1096 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_YLEN); in sirfsoc_dma_pm_resume()
1098 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_CTRL); in sirfsoc_dma_pm_resume()
1104 sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_ADDR); in sirfsoc_dma_pm_resume()
1113 return 0; in sirfsoc_dma_pm_resume()