1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
22 #include <linux/dma/pxa-dma.h>
25 #include "virt-dma.h"
36 #define PXA_DCSR_NODESC		BIT(30)	/* No-Descriptor Fetch (read / write) */
38 #define PXA_DCSR_REQPEND	BIT(8)	/* Request Pending (read-only) */
39 #define PXA_DCSR_STOPSTATE	BIT(3)	/* Stop State (read-only) */
64 #define PXA_DCMD_ENDIAN		BIT(18)	/* Device Endian-ness. */
71 #define PXA_DCMD_LENGTH		0x01fff		/* length mask (max = 8K - 1) */
74 #define PDMA_MAX_DESC_BYTES	(PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))
94 	struct pxad_desc_hw	*hw_desc[];	/* DMA coherent descriptors */
115 	/* protected by vc->lock */
146 	readl_relaxed((phy)->base + _reg((phy)->idx))
150 		_v = readl_relaxed((phy)->base + _reg((phy)->idx));	\
151 		dev_vdbg(&phy->vchan->vc.chan.dev->device,		\
158 		writel((val), (phy)->base + _reg((phy)->idx));		\
159 		dev_vdbg(&phy->vchan->vc.chan.dev->device,		\
165 		writel_relaxed((val), (phy)->base + _reg((phy)->idx));	\
166 		dev_vdbg(&phy->vchan->vc.chan.dev->device,		\
190 	struct pxad_phy *phy = s->private;  in requester_chan_show()
194 	seq_printf(s, "DMA channel %d requester :\n", phy->idx);  in requester_chan_show()
196 		drcmr = readl_relaxed(phy->base + pxad_drcmr(i));  in requester_chan_show()
197 		if ((drcmr & DRCMR_CHLNUM) == phy->idx)  in requester_chan_show()
221 	struct pxad_phy *phy = s->private;  in descriptors_show()
229 	seq_printf(s, "DMA channel %d descriptors :\n", phy->idx);  in descriptors_show()
233 		dcmd = desc->dcmd;  in descriptors_show()
239 		seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);  in descriptors_show()
240 		seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);  in descriptors_show()
241 		seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);  in descriptors_show()
249 		phys_desc = desc->ddadr;  in descriptors_show()
264 	struct pxad_phy *phy = s->private;  in chan_state_show()
276 	seq_printf(s, "DMA channel %d\n", phy->idx);  in chan_state_show()
278 			  str_prio[(phy->idx & 0xf) / 4]);  in chan_state_show()
280 			  _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ?  in chan_state_show()
307 	struct pxad_device *pdev = s->private;  in state_show()
310 	seq_puts(s, "DMA engine status\n");  in state_show()
311 	seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans);  in state_show()
330 	dt = (void *)&pdev->phys[ch];  in pxad_dbg_alloc_chan()
344 	pdev->dbgfs_chan =  in pxad_init_debugfs()
345 		kmalloc_array(pdev->nr_chans, sizeof(struct dentry *),  in pxad_init_debugfs()
347 	if (!pdev->dbgfs_chan)  in pxad_init_debugfs()
350 	pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL);  in pxad_init_debugfs()
352 	debugfs_create_file("state", 0400, pdev->dbgfs_root, pdev, &state_fops);  in pxad_init_debugfs()
354 	chandir = debugfs_create_dir("channels", pdev->dbgfs_root);  in pxad_init_debugfs()
356 	for (i = 0; i < pdev->nr_chans; i++)  in pxad_init_debugfs()
357 		pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir);  in pxad_init_debugfs()
362 	debugfs_remove_recursive(pdev->dbgfs_root);  in pxad_cleanup_debugfs()
372 	struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device);  in lookup_phy()
377 	 * dma channel priorities  in lookup_phy()
378 	 * ch 0 - 3,  16 - 19  <--> (0)  in lookup_phy()
379 	 * ch 4 - 7,  20 - 23  <--> (1)  in lookup_phy()
380 	 * ch 8 - 11, 24 - 27  <--> (2)  in lookup_phy()
381 	 * ch 12 - 15, 28 - 31  <--> (3)  in lookup_phy()
384 	spin_lock_irqsave(&pdev->phy_lock, flags);  in lookup_phy()
385 	for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) {  in lookup_phy()
386 		for (i = 0; i < pdev->nr_chans; i++) {  in lookup_phy()
389 			phy = &pdev->phys[i];  in lookup_phy()
390 			if (!phy->vchan) {  in lookup_phy()
391 				phy->vchan = pchan;  in lookup_phy()
399 	spin_unlock_irqrestore(&pdev->phy_lock, flags);  in lookup_phy()
400 	dev_dbg(&pchan->vc.chan.dev->device,  in lookup_phy()
402 		found ? found->idx : -1);  in lookup_phy()
409 	struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);  in pxad_free_phy()
413 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_free_phy()
415 	if (!chan->phy)  in pxad_free_phy()
419 	if (chan->drcmr <= pdev->nr_requestors) {  in pxad_free_phy()
420 		reg = pxad_drcmr(chan->drcmr);  in pxad_free_phy()
421 		writel_relaxed(0, chan->phy->base + reg);  in pxad_free_phy()
424 	spin_lock_irqsave(&pdev->phy_lock, flags);  in pxad_free_phy()
425 	chan->phy->vchan = NULL;  in pxad_free_phy()
426 	chan->phy = NULL;  in pxad_free_phy()
427 	spin_unlock_irqrestore(&pdev->phy_lock, flags);  in pxad_free_phy()
433 	struct pxad_phy *phy = chan->phy;  in is_chan_running()
445 	BUG_ON(!chan->phy);  in is_running_chan_misaligned()
446 	dalgn = phy_readl_relaxed(chan->phy, DALGN);  in is_running_chan_misaligned()
447 	return dalgn & (BIT(chan->phy->idx));  in is_running_chan_misaligned()
455 	if (!phy->vchan)  in phy_enable()
458 	dev_dbg(&phy->vchan->vc.chan.dev->device,  in phy_enable()
460 		phy, phy->idx, misaligned);  in phy_enable()
462 	pdev = to_pxad_dev(phy->vchan->vc.chan.device);  in phy_enable()
463 	if (phy->vchan->drcmr <= pdev->nr_requestors) {  in phy_enable()
464 		reg = pxad_drcmr(phy->vchan->drcmr);  in phy_enable()
465 		writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg);  in phy_enable()
470 		dalgn |= BIT(phy->idx);  in phy_enable()
472 		dalgn &= ~BIT(phy->idx);  in phy_enable()
487 	dev_dbg(&phy->vchan->vc.chan.dev->device,  in phy_disable()
488 		"%s(): phy=%p(%d)\n", __func__, phy, phy->idx);  in phy_disable()
495 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_launch_chan()
497 	if (!chan->phy) {  in pxad_launch_chan()
498 		chan->phy = lookup_phy(chan);  in pxad_launch_chan()
499 		if (!chan->phy) {  in pxad_launch_chan()
500 			dev_dbg(&chan->vc.chan.dev->device,  in pxad_launch_chan()
501 				"%s(): no free dma channel\n", __func__);  in pxad_launch_chan()
505 	chan->bus_error = 0;  in pxad_launch_chan()
508 	 * Program the descriptor's address into the DMA controller,  in pxad_launch_chan()
509 	 * then start the DMA transaction  in pxad_launch_chan()
511 	phy_writel(chan->phy, desc->first, DDADR);  in pxad_launch_chan()
512 	phy_enable(chan->phy, chan->misaligned);  in pxad_launch_chan()
513 	wake_up(&chan->wq_state);  in pxad_launch_chan()
520 		sw_desc->hw_desc[sw_desc->nb_desc - 1];  in set_updater_desc()
521 	dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr;  in set_updater_desc()  local
523 	updater->ddadr = DDADR_STOP;  in set_updater_desc()
524 	updater->dsadr = dma;  in set_updater_desc()
525 	updater->dtadr = dma + 8;  in set_updater_desc()
526 	updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 |  in set_updater_desc()
529 		updater->dcmd |= PXA_DCMD_ENDIRQEN;  in set_updater_desc()
530 	if (sw_desc->cyclic)  in set_updater_desc()
531 		sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first;  in set_updater_desc()
538 		sw_desc->hw_desc[sw_desc->nb_desc - 1];  in is_desc_completed()
540 	return updater->dtadr != (updater->dsadr + 8);  in is_desc_completed()
550 	dma_to_chain = desc2->first;  in pxad_desc_chain()
551 	desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain;  in pxad_desc_chain()
558 	struct pxad_chan *chan = to_pxad_chan(&vc->chan);  in pxad_try_hotchain()
568 		BUG_ON(list_empty(&vc->desc_issued));  in pxad_try_hotchain()
571 		    to_pxad_sw_desc(vd)->misaligned)  in pxad_try_hotchain()
574 		vd_last_issued = list_entry(vc->desc_issued.prev,  in pxad_try_hotchain()
587 	u32 dint = readl(phy->base + DINT);  in clear_chan_irq()
589 	if (!(dint & BIT(phy->idx)))  in clear_chan_irq()
595 	if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan))  in clear_chan_irq()
596 		dev_warn(&phy->vchan->vc.chan.dev->device,  in clear_chan_irq()
598 			 __func__, &phy->vchan);  in clear_chan_irq()
606 	struct pxad_chan *chan = phy->vchan;  in pxad_chan_handler()
619 	spin_lock_irqsave(&chan->vc.lock, flags);  in pxad_chan_handler()
620 	list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) {  in pxad_chan_handler()
622 		dev_dbg(&chan->vc.chan.dev->device,  in pxad_chan_handler()
624 			__func__, vd, vd->tx.cookie, vd_completed,  in pxad_chan_handler()
626 		last_started = vd->tx.cookie;  in pxad_chan_handler()
627 		if (to_pxad_sw_desc(vd)->cyclic) {  in pxad_chan_handler()
632 			list_del(&vd->node);  in pxad_chan_handler()
640 		chan->bus_error = last_started;  in pxad_chan_handler()
644 	if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) {  in pxad_chan_handler()
645 		dev_dbg(&chan->vc.chan.dev->device,  in pxad_chan_handler()
648 			list_empty(&chan->vc.desc_submitted),  in pxad_chan_handler()
649 			list_empty(&chan->vc.desc_issued));  in pxad_chan_handler()
652 		if (list_empty(&chan->vc.desc_issued)) {  in pxad_chan_handler()
653 			chan->misaligned =  in pxad_chan_handler()
654 				!list_empty(&chan->vc.desc_submitted);  in pxad_chan_handler()
656 			vd = list_first_entry(&chan->vc.desc_issued,  in pxad_chan_handler()
661 	spin_unlock_irqrestore(&chan->vc.lock, flags);  in pxad_chan_handler()
662 	wake_up(&chan->wq_state);  in pxad_chan_handler()
671 	u32 dint = readl(pdev->base + DINT);  in pxad_int_handler()
676 		dint &= (dint - 1);  in pxad_int_handler()
677 		phy = &pdev->phys[i];  in pxad_int_handler()
688 	struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);  in pxad_alloc_chan_resources()
690 	if (chan->desc_pool)  in pxad_alloc_chan_resources()
693 	chan->desc_pool = dma_pool_create(dma_chan_name(dchan),  in pxad_alloc_chan_resources()
694 					  pdev->slave.dev,  in pxad_alloc_chan_resources()
698 	if (!chan->desc_pool) {  in pxad_alloc_chan_resources()
699 		dev_err(&chan->vc.chan.dev->device,  in pxad_alloc_chan_resources()
702 		return -ENOMEM;  in pxad_alloc_chan_resources()
712 	vchan_free_chan_resources(&chan->vc);  in pxad_free_chan_resources()
713 	dma_pool_destroy(chan->desc_pool);  in pxad_free_chan_resources()
714 	chan->desc_pool = NULL;  in pxad_free_chan_resources()
716 	chan->drcmr = U32_MAX;  in pxad_free_chan_resources()
717 	chan->prio = PXAD_PRIO_LOWEST;  in pxad_free_chan_resources()
723 	dma_addr_t dma;  in pxad_free_desc()  local
726 	BUG_ON(sw_desc->nb_desc == 0);  in pxad_free_desc()
727 	for (i = sw_desc->nb_desc - 1; i >= 0; i--) {  in pxad_free_desc()
729 			dma = sw_desc->hw_desc[i - 1]->ddadr;  in pxad_free_desc()
731 			dma = sw_desc->first;  in pxad_free_desc()
732 		dma_pool_free(sw_desc->desc_pool,  in pxad_free_desc()
733 			      sw_desc->hw_desc[i], dma);  in pxad_free_desc()
735 	sw_desc->nb_desc = 0;  in pxad_free_desc()
743 	dma_addr_t dma;  in pxad_alloc_desc()  local
751 	sw_desc->desc_pool = chan->desc_pool;  in pxad_alloc_desc()
754 		sw_desc->hw_desc[i] = dma_pool_alloc(sw_desc->desc_pool,  in pxad_alloc_desc()
755 						     GFP_NOWAIT, &dma);  in pxad_alloc_desc()
756 		if (!sw_desc->hw_desc[i]) {  in pxad_alloc_desc()
757 			dev_err(&chan->vc.chan.dev->device,  in pxad_alloc_desc()
759 				__func__, i, sw_desc->desc_pool);  in pxad_alloc_desc()
764 			sw_desc->first = dma;  in pxad_alloc_desc()
766 			sw_desc->hw_desc[i - 1]->ddadr = dma;  in pxad_alloc_desc()
767 		sw_desc->nb_desc++;  in pxad_alloc_desc()
772 	pxad_free_desc(&sw_desc->vd);  in pxad_alloc_desc()
778 	struct virt_dma_chan *vc = to_virt_chan(tx->chan);  in pxad_tx_submit()
779 	struct pxad_chan *chan = to_pxad_chan(&vc->chan);  in pxad_tx_submit()
785 	set_updater_desc(to_pxad_sw_desc(vd), tx->flags);  in pxad_tx_submit()
787 	spin_lock_irqsave(&vc->lock, flags);  in pxad_tx_submit()
790 	if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) {  in pxad_tx_submit()
791 		list_move_tail(&vd->node, &vc->desc_issued);  in pxad_tx_submit()
792 		dev_dbg(&chan->vc.chan.dev->device,  in pxad_tx_submit()
801 	if (!list_empty(&vc->desc_submitted)) {  in pxad_tx_submit()
802 		vd_chained = list_entry(vc->desc_submitted.prev,  in pxad_tx_submit()
810 		if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned)  in pxad_tx_submit()
815 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_tx_submit()
818 	list_move_tail(&vd->node, &vc->desc_submitted);  in pxad_tx_submit()
819 	chan->misaligned |= to_pxad_sw_desc(vd)->misaligned;  in pxad_tx_submit()
822 	spin_unlock_irqrestore(&vc->lock, flags);  in pxad_tx_submit()
832 	spin_lock_irqsave(&chan->vc.lock, flags);  in pxad_issue_pending()
833 	if (list_empty(&chan->vc.desc_submitted))  in pxad_issue_pending()
836 	vd_first = list_first_entry(&chan->vc.desc_submitted,  in pxad_issue_pending()
838 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_issue_pending()
839 		"%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie);  in pxad_issue_pending()
841 	vchan_issue_pending(&chan->vc);  in pxad_issue_pending()
842 	if (!pxad_try_hotchain(&chan->vc, vd_first))  in pxad_issue_pending()
845 	spin_unlock_irqrestore(&chan->vc.lock, flags);  in pxad_issue_pending()
855 	INIT_LIST_HEAD(&vd->node);  in pxad_tx_prep()
857 	tx->tx_submit = pxad_tx_submit;  in pxad_tx_prep()
858 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_tx_prep()
860 		vc, vd, vd->tx.cookie,  in pxad_tx_prep()
870 	u32 maxburst = 0, dev_addr = 0;  in pxad_get_config()  local
872 	struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);  in pxad_get_config()
876 		maxburst = chan->cfg.src_maxburst;  in pxad_get_config()
877 		width = chan->cfg.src_addr_width;  in pxad_get_config()
878 		dev_addr = chan->cfg.src_addr;  in pxad_get_config()
881 		if (chan->drcmr <= pdev->nr_requestors)  in pxad_get_config()
885 		maxburst = chan->cfg.dst_maxburst;  in pxad_get_config()
886 		width = chan->cfg.dst_addr_width;  in pxad_get_config()
887 		dev_addr = chan->cfg.dst_addr;  in pxad_get_config()
890 		if (chan->drcmr <= pdev->nr_requestors)  in pxad_get_config()
897 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_get_config()
898 		"%s(): dev_addr=0x%x maxburst=%d width=%d  dir=%d\n",  in pxad_get_config()
899 		__func__, dev_addr, maxburst, width, dir);  in pxad_get_config()
908 	if (maxburst == 8)  in pxad_get_config()
910 	else if (maxburst == 16)  in pxad_get_config()
912 	else if (maxburst == 32)  in pxad_get_config()
919 	if (chan->cfg.slave_id)  in pxad_get_config()
920 		chan->drcmr = chan->cfg.slave_id;  in pxad_get_config()
938 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_prep_memcpy()
948 	sw_desc->len = len;  in pxad_prep_memcpy()
952 		sw_desc->misaligned = true;  in pxad_prep_memcpy()
956 		hw_desc = sw_desc->hw_desc[i++];  in pxad_prep_memcpy()
958 		hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy);  in pxad_prep_memcpy()
959 		hw_desc->dsadr = dma_src;  in pxad_prep_memcpy()
960 		hw_desc->dtadr = dma_dst;  in pxad_prep_memcpy()
961 		len -= copy;  in pxad_prep_memcpy()
967 	return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);  in pxad_prep_memcpy()
979 	dma_addr_t dma;  in pxad_prep_slave_sg()  local
987 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_prep_slave_sg()
997 		dma = sg_dma_address(sg);  in pxad_prep_slave_sg()
999 		sw_desc->len += avail;  in pxad_prep_slave_sg()
1003 			if (dma & 0x7)  in pxad_prep_slave_sg()
1004 				sw_desc->misaligned = true;  in pxad_prep_slave_sg()
1006 			sw_desc->hw_desc[j]->dcmd =  in pxad_prep_slave_sg()
1008 			sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma;  in pxad_prep_slave_sg()
1009 			sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma;  in pxad_prep_slave_sg()
1011 			dma += len;  in pxad_prep_slave_sg()
1012 			avail -= len;  in pxad_prep_slave_sg()
1017 	return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);  in pxad_prep_slave_sg()
1028 	dma_addr_t dma;  in pxad_prep_dma_cyclic()  local
1035 		dev_err(&chan->vc.chan.dev->device,  in pxad_prep_dma_cyclic()
1036 			"Unsupported direction for cyclic DMA\n");  in pxad_prep_dma_cyclic()
1046 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_prep_dma_cyclic()
1055 	sw_desc->cyclic = true;  in pxad_prep_dma_cyclic()
1056 	sw_desc->len = len;  in pxad_prep_dma_cyclic()
1058 	phw_desc = sw_desc->hw_desc;  in pxad_prep_dma_cyclic()
1059 	dma = buf_addr;  in pxad_prep_dma_cyclic()
1061 		phw_desc[0]->dsadr = dsadr ? dsadr : dma;  in pxad_prep_dma_cyclic()
1062 		phw_desc[0]->dtadr = dtadr ? dtadr : dma;  in pxad_prep_dma_cyclic()
1063 		phw_desc[0]->dcmd = dcmd;  in pxad_prep_dma_cyclic()
1065 		dma += period_len;  in pxad_prep_dma_cyclic()
1066 		len -= period_len;  in pxad_prep_dma_cyclic()
1070 	return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);  in pxad_prep_dma_cyclic()
1079 		return -EINVAL;  in pxad_config()
1081 	chan->cfg = *cfg;  in pxad_config()
1088 	struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);  in pxad_terminate_all()
1094 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_terminate_all()
1095 		"%s(): vchan %p: terminate all\n", __func__, &chan->vc);  in pxad_terminate_all()
1097 	spin_lock_irqsave(&chan->vc.lock, flags);  in pxad_terminate_all()
1098 	vchan_get_all_descriptors(&chan->vc, &head);  in pxad_terminate_all()
1101 		dev_dbg(&chan->vc.chan.dev->device,  in pxad_terminate_all()
1103 			vd, vd->tx.cookie, is_desc_completed(vd));  in pxad_terminate_all()
1106 	phy = chan->phy;  in pxad_terminate_all()
1108 		phy_disable(chan->phy);  in pxad_terminate_all()
1110 		chan->phy = NULL;  in pxad_terminate_all()
1111 		spin_lock(&pdev->phy_lock);  in pxad_terminate_all()
1112 		phy->vchan = NULL;  in pxad_terminate_all()
1113 		spin_unlock(&pdev->phy_lock);  in pxad_terminate_all()
1115 	spin_unlock_irqrestore(&chan->vc.lock, flags);  in pxad_terminate_all()
1116 	vchan_dma_desc_free_list(&chan->vc, &head);  in pxad_terminate_all()
1136 	if (!chan->phy)  in pxad_residue()
1139 	spin_lock_irqsave(&chan->vc.lock, flags);  in pxad_residue()
1141 	vd = vchan_find_desc(&chan->vc, cookie);  in pxad_residue()
1146 	if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)  in pxad_residue()
1147 		curr = phy_readl_relaxed(chan->phy, DSADR);  in pxad_residue()
1149 		curr = phy_readl_relaxed(chan->phy, DTADR);  in pxad_residue()
1161 	for (i = 0; i < sw_desc->nb_desc - 1; i++) {  in pxad_residue()
1162 		hw_desc = sw_desc->hw_desc[i];  in pxad_residue()
1163 		if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)  in pxad_residue()
1164 			start = hw_desc->dsadr;  in pxad_residue()
1166 			start = hw_desc->dtadr;  in pxad_residue()
1167 		len = hw_desc->dcmd & PXA_DCMD_LENGTH;  in pxad_residue()
1182 			residue += end - curr;  in pxad_residue()
1187 		residue = sw_desc->len;  in pxad_residue()
1190 	spin_unlock_irqrestore(&chan->vc.lock, flags);  in pxad_residue()
1191 	dev_dbg(&chan->vc.chan.dev->device,  in pxad_residue()
1204 	if (cookie == chan->bus_error)  in pxad_tx_status()
1218 	wait_event(chan->wq_state, !is_chan_running(chan));  in pxad_synchronize()
1219 	vchan_synchronize(&chan->vc);  in pxad_synchronize()
1226 	list_for_each_entry_safe(c, cn, &dmadev->channels,  in pxad_free_channels()
1228 		list_del(&c->vc.chan.device_node);  in pxad_free_channels()
1229 		tasklet_kill(&c->vc.task);  in pxad_free_channels()
1238 	pxad_free_channels(&pdev->slave);  in pxad_remove()
1253 	pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans,  in pxad_init_phys()
1254 				  sizeof(pdev->phys[0]), GFP_KERNEL);  in pxad_init_phys()
1255 	if (!pdev->phys)  in pxad_init_phys()
1256 		return -ENOMEM;  in pxad_init_phys()
1263 		phy = &pdev->phys[i];  in pxad_init_phys()
1264 		phy->base = pdev->base;  in pxad_init_phys()
1265 		phy->idx = i;  in pxad_init_phys()
1268 			ret = devm_request_irq(&op->dev, irq,  in pxad_init_phys()
1270 					       IRQF_SHARED, "pxa-dma", phy);  in pxad_init_phys()
1272 			ret = devm_request_irq(&op->dev, irq0,  in pxad_init_phys()
1274 					       IRQF_SHARED, "pxa-dma", pdev);  in pxad_init_phys()
1276 			dev_err(pdev->slave.dev,  in pxad_init_phys()
1287 	{ .compatible = "marvell,pdma-1.0", },
1295 	struct pxad_device *d = ofdma->of_dma_data;  in pxad_dma_xlate()
1298 	chan = dma_get_any_slave_channel(&d->slave);  in pxad_dma_xlate()
1302 	to_pxad_chan(chan)->drcmr = dma_spec->args[0];  in pxad_dma_xlate()
1303 	to_pxad_chan(chan)->prio = dma_spec->args[1];  in pxad_dma_xlate()
1317 	pdev->nr_chans = nr_phy_chans;  in pxad_init_dmadev()
1318 	pdev->nr_requestors = nr_requestors;  in pxad_init_dmadev()
1319 	INIT_LIST_HEAD(&pdev->slave.channels);  in pxad_init_dmadev()
1320 	pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources;  in pxad_init_dmadev()
1321 	pdev->slave.device_free_chan_resources = pxad_free_chan_resources;  in pxad_init_dmadev()
1322 	pdev->slave.device_tx_status = pxad_tx_status;  in pxad_init_dmadev()
1323 	pdev->slave.device_issue_pending = pxad_issue_pending;  in pxad_init_dmadev()
1324 	pdev->slave.device_config = pxad_config;  in pxad_init_dmadev()
1325 	pdev->slave.device_synchronize = pxad_synchronize;  in pxad_init_dmadev()
1326 	pdev->slave.device_terminate_all = pxad_terminate_all;  in pxad_init_dmadev()
1328 	if (op->dev.coherent_dma_mask)  in pxad_init_dmadev()
1329 		dma_set_mask(&op->dev, op->dev.coherent_dma_mask);  in pxad_init_dmadev()
1331 		dma_set_mask(&op->dev, DMA_BIT_MASK(32));  in pxad_init_dmadev()
1338 		c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL);  in pxad_init_dmadev()
1340 			return -ENOMEM;  in pxad_init_dmadev()
1342 		c->drcmr = U32_MAX;  in pxad_init_dmadev()
1343 		c->prio = PXAD_PRIO_LOWEST;  in pxad_init_dmadev()
1344 		c->vc.desc_free = pxad_free_desc;  in pxad_init_dmadev()
1345 		vchan_init(&c->vc, &pdev->slave);  in pxad_init_dmadev()
1346 		init_waitqueue_head(&c->wq_state);  in pxad_init_dmadev()
1349 	return dmaenginem_async_device_register(&pdev->slave);  in pxad_init_dmadev()
1357 	struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);  in pxad_probe()
1364 	pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);  in pxad_probe()
1366 		return -ENOMEM;  in pxad_probe()
1368 	spin_lock_init(&pdev->phy_lock);  in pxad_probe()
1371 	pdev->base = devm_ioremap_resource(&op->dev, iores);  in pxad_probe()
1372 	if (IS_ERR(pdev->base))  in pxad_probe()
1373 		return PTR_ERR(pdev->base);  in pxad_probe()
1375 	of_id = of_match_device(pxad_dt_ids, &op->dev);  in pxad_probe()
1377 		of_property_read_u32(op->dev.of_node, "#dma-channels",  in pxad_probe()
1379 		ret = of_property_read_u32(op->dev.of_node, "#dma-requests",  in pxad_probe()
1382 			dev_warn(pdev->slave.dev,  in pxad_probe()
1383 				 "#dma-requests set to default 32 as missing in OF: %d",  in pxad_probe()
1387 	} else if (pdata && pdata->dma_channels) {  in pxad_probe()
1388 		dma_channels = pdata->dma_channels;  in pxad_probe()
1389 		nb_requestors = pdata->nb_requestors;  in pxad_probe()
1390 		slave_map = pdata->slave_map;  in pxad_probe()
1391 		slave_map_cnt = pdata->slave_map_cnt;  in pxad_probe()
1396 	dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask);  in pxad_probe()
1397 	dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask);  in pxad_probe()
1398 	dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask);  in pxad_probe()
1399 	dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask);  in pxad_probe()
1400 	pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy;  in pxad_probe()
1401 	pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg;  in pxad_probe()
1402 	pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic;  in pxad_probe()
1403 	pdev->slave.filter.map = slave_map;  in pxad_probe()
1404 	pdev->slave.filter.mapcnt = slave_map_cnt;  in pxad_probe()
1405 	pdev->slave.filter.fn = pxad_filter_fn;  in pxad_probe()
1407 	pdev->slave.copy_align = PDMA_ALIGNMENT;  in pxad_probe()
1408 	pdev->slave.src_addr_widths = widths;  in pxad_probe()
1409 	pdev->slave.dst_addr_widths = widths;  in pxad_probe()
1410 	pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);  in pxad_probe()
1411 	pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;  in pxad_probe()
1412 	pdev->slave.descriptor_reuse = true;  in pxad_probe()
1414 	pdev->slave.dev = &op->dev;  in pxad_probe()
1417 		dev_err(pdev->slave.dev, "unable to register\n");  in pxad_probe()
1421 	if (op->dev.of_node) {  in pxad_probe()
1422 		/* Device-tree DMA controller registration */  in pxad_probe()
1423 		ret = of_dma_controller_register(op->dev.of_node,  in pxad_probe()
1426 			dev_err(pdev->slave.dev,  in pxad_probe()
1434 	dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n",  in pxad_probe()
1440 	{ "pxa-dma", },
1446 		.name	= "pxa-dma",
1459 	if (chan->device->dev->driver != &pxad_driver.driver)  in pxad_filter_fn()
1462 	c->drcmr = p->drcmr;  in pxad_filter_fn()
1463 	c->prio = p->prio;  in pxad_filter_fn()
1470 MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver");