Lines Matching +full:dma +full:- +full:maxburst
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
21 #include <linux/dma/mmp-pdma.h>
34 #define DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
36 #define DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
37 #define DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
63 #define DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
70 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
147 u32 reg = (phy->idx << 4) + DDADR; in set_desc()
149 writel(addr, phy->base + reg); in set_desc()
156 if (!phy->vchan) in enable_chan()
159 reg = DRCMR(phy->vchan->drcmr); in enable_chan()
160 writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); in enable_chan()
162 dalgn = readl(phy->base + DALGN); in enable_chan()
163 if (phy->vchan->byte_align) in enable_chan()
164 dalgn |= 1 << phy->idx; in enable_chan()
166 dalgn &= ~(1 << phy->idx); in enable_chan()
167 writel(dalgn, phy->base + DALGN); in enable_chan()
169 reg = (phy->idx << 2) + DCSR; in enable_chan()
170 writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg); in enable_chan()
180 reg = (phy->idx << 2) + DCSR; in disable_chan()
181 writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg); in disable_chan()
187 u32 dint = readl(phy->base + DINT); in clear_chan_irq()
188 u32 reg = (phy->idx << 2) + DCSR; in clear_chan_irq()
190 if (!(dint & BIT(phy->idx))) in clear_chan_irq()
191 return -EAGAIN; in clear_chan_irq()
194 dcsr = readl(phy->base + reg); in clear_chan_irq()
195 writel(dcsr, phy->base + reg); in clear_chan_irq()
196 if ((dcsr & DCSR_BUSERR) && (phy->vchan)) in clear_chan_irq()
197 dev_warn(phy->vchan->dev, "DCSR_BUSERR\n"); in clear_chan_irq()
209 tasklet_schedule(&phy->vchan->tasklet); in mmp_pdma_chan_handler()
217 u32 dint = readl(pdev->base + DINT); in mmp_pdma_int_handler()
224 if (i >= pdev->dma_channels) in mmp_pdma_int_handler()
226 dint &= (dint - 1); in mmp_pdma_int_handler()
227 phy = &pdev->phy[i]; in mmp_pdma_int_handler()
243 struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device); in lookup_phy()
248 * dma channel priorities in lookup_phy()
249 * ch 0 - 3, 16 - 19 <--> (0) in lookup_phy()
250 * ch 4 - 7, 20 - 23 <--> (1) in lookup_phy()
251 * ch 8 - 11, 24 - 27 <--> (2) in lookup_phy()
252 * ch 12 - 15, 28 - 31 <--> (3) in lookup_phy()
255 spin_lock_irqsave(&pdev->phy_lock, flags); in lookup_phy()
256 for (prio = 0; prio <= ((pdev->dma_channels - 1) & 0xf) >> 2; prio++) { in lookup_phy()
257 for (i = 0; i < pdev->dma_channels; i++) { in lookup_phy()
260 phy = &pdev->phy[i]; in lookup_phy()
261 if (!phy->vchan) { in lookup_phy()
262 phy->vchan = pchan; in lookup_phy()
270 spin_unlock_irqrestore(&pdev->phy_lock, flags); in lookup_phy()
276 struct mmp_pdma_device *pdev = to_mmp_pdma_dev(pchan->chan.device); in mmp_pdma_free_phy()
280 if (!pchan->phy) in mmp_pdma_free_phy()
284 reg = DRCMR(pchan->drcmr); in mmp_pdma_free_phy()
285 writel(0, pchan->phy->base + reg); in mmp_pdma_free_phy()
287 spin_lock_irqsave(&pdev->phy_lock, flags); in mmp_pdma_free_phy()
288 pchan->phy->vchan = NULL; in mmp_pdma_free_phy()
289 pchan->phy = NULL; in mmp_pdma_free_phy()
290 spin_unlock_irqrestore(&pdev->phy_lock, flags); in mmp_pdma_free_phy()
294 * start_pending_queue - transfer any pending transactions
302 if (!chan->idle) { in start_pending_queue()
303 dev_dbg(chan->dev, "DMA controller still busy\n"); in start_pending_queue()
307 if (list_empty(&chan->chain_pending)) { in start_pending_queue()
308 /* chance to re-fetch phy channel with higher prio */ in start_pending_queue()
310 dev_dbg(chan->dev, "no pending list\n"); in start_pending_queue()
314 if (!chan->phy) { in start_pending_queue()
315 chan->phy = lookup_phy(chan); in start_pending_queue()
316 if (!chan->phy) { in start_pending_queue()
317 dev_dbg(chan->dev, "no free dma channel\n"); in start_pending_queue()
323 * pending -> running in start_pending_queue()
326 desc = list_first_entry(&chan->chain_pending, in start_pending_queue()
328 list_splice_tail_init(&chan->chain_pending, &chan->chain_running); in start_pending_queue()
331 * Program the descriptor's address into the DMA controller, in start_pending_queue()
332 * then start the DMA transaction in start_pending_queue()
334 set_desc(chan->phy, desc->async_tx.phys); in start_pending_queue()
335 enable_chan(chan->phy); in start_pending_queue()
336 chan->idle = false; in start_pending_queue()
340 /* desc->tx_list ==> pending list */
343 struct mmp_pdma_chan *chan = to_mmp_pdma_chan(tx->chan); in mmp_pdma_tx_submit()
347 dma_cookie_t cookie = -EBUSY; in mmp_pdma_tx_submit()
349 spin_lock_irqsave(&chan->desc_lock, flags); in mmp_pdma_tx_submit()
351 list_for_each_entry(child, &desc->tx_list, node) { in mmp_pdma_tx_submit()
352 cookie = dma_cookie_assign(&child->async_tx); in mmp_pdma_tx_submit()
355 /* softly link to pending list - desc->tx_list ==> pending list */ in mmp_pdma_tx_submit()
356 list_splice_tail_init(&desc->tx_list, &chan->chain_pending); in mmp_pdma_tx_submit()
358 spin_unlock_irqrestore(&chan->desc_lock, flags); in mmp_pdma_tx_submit()
369 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc); in mmp_pdma_alloc_descriptor()
371 dev_err(chan->dev, "out of memory for link descriptor\n"); in mmp_pdma_alloc_descriptor()
375 INIT_LIST_HEAD(&desc->tx_list); in mmp_pdma_alloc_descriptor()
376 dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan); in mmp_pdma_alloc_descriptor()
378 desc->async_tx.tx_submit = mmp_pdma_tx_submit; in mmp_pdma_alloc_descriptor()
379 desc->async_tx.phys = pdesc; in mmp_pdma_alloc_descriptor()
385 * mmp_pdma_alloc_chan_resources - Allocate resources for DMA channel.
387 * This function will create a dma pool for descriptor allocation.
389 * Return - The number of allocated descriptors.
396 if (chan->desc_pool) in mmp_pdma_alloc_chan_resources()
399 chan->desc_pool = dma_pool_create(dev_name(&dchan->dev->device), in mmp_pdma_alloc_chan_resources()
400 chan->dev, in mmp_pdma_alloc_chan_resources()
404 if (!chan->desc_pool) { in mmp_pdma_alloc_chan_resources()
405 dev_err(chan->dev, "unable to allocate descriptor pool\n"); in mmp_pdma_alloc_chan_resources()
406 return -ENOMEM; in mmp_pdma_alloc_chan_resources()
410 chan->idle = true; in mmp_pdma_alloc_chan_resources()
411 chan->dev_addr = 0; in mmp_pdma_alloc_chan_resources()
421 list_del(&desc->node); in mmp_pdma_free_desc_list()
422 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); in mmp_pdma_free_desc_list()
431 spin_lock_irqsave(&chan->desc_lock, flags); in mmp_pdma_free_chan_resources()
432 mmp_pdma_free_desc_list(chan, &chan->chain_pending); in mmp_pdma_free_chan_resources()
433 mmp_pdma_free_desc_list(chan, &chan->chain_running); in mmp_pdma_free_chan_resources()
434 spin_unlock_irqrestore(&chan->desc_lock, flags); in mmp_pdma_free_chan_resources()
436 dma_pool_destroy(chan->desc_pool); in mmp_pdma_free_chan_resources()
437 chan->desc_pool = NULL; in mmp_pdma_free_chan_resources()
438 chan->idle = true; in mmp_pdma_free_chan_resources()
439 chan->dev_addr = 0; in mmp_pdma_free_chan_resources()
460 chan->byte_align = false; in mmp_pdma_prep_memcpy()
462 if (!chan->dir) { in mmp_pdma_prep_memcpy()
463 chan->dir = DMA_MEM_TO_MEM; in mmp_pdma_prep_memcpy()
464 chan->dcmd = DCMD_INCTRGADDR | DCMD_INCSRCADDR; in mmp_pdma_prep_memcpy()
465 chan->dcmd |= DCMD_BURST32; in mmp_pdma_prep_memcpy()
469 /* Allocate the link descriptor from DMA pool */ in mmp_pdma_prep_memcpy()
472 dev_err(chan->dev, "no memory for desc\n"); in mmp_pdma_prep_memcpy()
478 chan->byte_align = true; in mmp_pdma_prep_memcpy()
480 new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & copy); in mmp_pdma_prep_memcpy()
481 new->desc.dsadr = dma_src; in mmp_pdma_prep_memcpy()
482 new->desc.dtadr = dma_dst; in mmp_pdma_prep_memcpy()
487 prev->desc.ddadr = new->async_tx.phys; in mmp_pdma_prep_memcpy()
489 new->async_tx.cookie = 0; in mmp_pdma_prep_memcpy()
490 async_tx_ack(&new->async_tx); in mmp_pdma_prep_memcpy()
493 len -= copy; in mmp_pdma_prep_memcpy()
495 if (chan->dir == DMA_MEM_TO_DEV) { in mmp_pdma_prep_memcpy()
497 } else if (chan->dir == DMA_DEV_TO_MEM) { in mmp_pdma_prep_memcpy()
499 } else if (chan->dir == DMA_MEM_TO_MEM) { in mmp_pdma_prep_memcpy()
505 list_add_tail(&new->node, &first->tx_list); in mmp_pdma_prep_memcpy()
508 first->async_tx.flags = flags; /* client is in control of this ack */ in mmp_pdma_prep_memcpy()
509 first->async_tx.cookie = -EBUSY; in mmp_pdma_prep_memcpy()
512 new->desc.ddadr = DDADR_STOP; in mmp_pdma_prep_memcpy()
513 new->desc.dcmd |= DCMD_ENDIRQEN; in mmp_pdma_prep_memcpy()
515 chan->cyclic_first = NULL; in mmp_pdma_prep_memcpy()
517 return &first->async_tx; in mmp_pdma_prep_memcpy()
521 mmp_pdma_free_desc_list(chan, &first->tx_list); in mmp_pdma_prep_memcpy()
540 chan->byte_align = false; in mmp_pdma_prep_slave_sg()
542 mmp_pdma_config_write(dchan, &chan->slave_config, dir); in mmp_pdma_prep_slave_sg()
551 chan->byte_align = true; in mmp_pdma_prep_slave_sg()
556 dev_err(chan->dev, "no memory for desc\n"); in mmp_pdma_prep_slave_sg()
560 new->desc.dcmd = chan->dcmd | (DCMD_LENGTH & len); in mmp_pdma_prep_slave_sg()
562 new->desc.dsadr = addr; in mmp_pdma_prep_slave_sg()
563 new->desc.dtadr = chan->dev_addr; in mmp_pdma_prep_slave_sg()
565 new->desc.dsadr = chan->dev_addr; in mmp_pdma_prep_slave_sg()
566 new->desc.dtadr = addr; in mmp_pdma_prep_slave_sg()
572 prev->desc.ddadr = new->async_tx.phys; in mmp_pdma_prep_slave_sg()
574 new->async_tx.cookie = 0; in mmp_pdma_prep_slave_sg()
575 async_tx_ack(&new->async_tx); in mmp_pdma_prep_slave_sg()
579 list_add_tail(&new->node, &first->tx_list); in mmp_pdma_prep_slave_sg()
583 avail -= len; in mmp_pdma_prep_slave_sg()
587 first->async_tx.cookie = -EBUSY; in mmp_pdma_prep_slave_sg()
588 first->async_tx.flags = flags; in mmp_pdma_prep_slave_sg()
591 new->desc.ddadr = DDADR_STOP; in mmp_pdma_prep_slave_sg()
592 new->desc.dcmd |= DCMD_ENDIRQEN; in mmp_pdma_prep_slave_sg()
594 chan->dir = dir; in mmp_pdma_prep_slave_sg()
595 chan->cyclic_first = NULL; in mmp_pdma_prep_slave_sg()
597 return &first->async_tx; in mmp_pdma_prep_slave_sg()
601 mmp_pdma_free_desc_list(chan, &first->tx_list); in mmp_pdma_prep_slave_sg()
626 mmp_pdma_config_write(dchan, &chan->slave_config, direction); in mmp_pdma_prep_dma_cyclic()
631 dma_dst = chan->dev_addr; in mmp_pdma_prep_dma_cyclic()
635 dma_src = chan->dev_addr; in mmp_pdma_prep_dma_cyclic()
638 dev_err(chan->dev, "Unsupported direction for cyclic DMA\n"); in mmp_pdma_prep_dma_cyclic()
642 chan->dir = direction; in mmp_pdma_prep_dma_cyclic()
645 /* Allocate the link descriptor from DMA pool */ in mmp_pdma_prep_dma_cyclic()
648 dev_err(chan->dev, "no memory for desc\n"); in mmp_pdma_prep_dma_cyclic()
652 new->desc.dcmd = (chan->dcmd | DCMD_ENDIRQEN | in mmp_pdma_prep_dma_cyclic()
654 new->desc.dsadr = dma_src; in mmp_pdma_prep_dma_cyclic()
655 new->desc.dtadr = dma_dst; in mmp_pdma_prep_dma_cyclic()
660 prev->desc.ddadr = new->async_tx.phys; in mmp_pdma_prep_dma_cyclic()
662 new->async_tx.cookie = 0; in mmp_pdma_prep_dma_cyclic()
663 async_tx_ack(&new->async_tx); in mmp_pdma_prep_dma_cyclic()
666 len -= period_len; in mmp_pdma_prep_dma_cyclic()
668 if (chan->dir == DMA_MEM_TO_DEV) in mmp_pdma_prep_dma_cyclic()
674 list_add_tail(&new->node, &first->tx_list); in mmp_pdma_prep_dma_cyclic()
677 first->async_tx.flags = flags; /* client is in control of this ack */ in mmp_pdma_prep_dma_cyclic()
678 first->async_tx.cookie = -EBUSY; in mmp_pdma_prep_dma_cyclic()
681 new->desc.ddadr = first->async_tx.phys; in mmp_pdma_prep_dma_cyclic()
682 chan->cyclic_first = first; in mmp_pdma_prep_dma_cyclic()
684 return &first->async_tx; in mmp_pdma_prep_dma_cyclic()
688 mmp_pdma_free_desc_list(chan, &first->tx_list); in mmp_pdma_prep_dma_cyclic()
697 u32 maxburst = 0, addr = 0; in mmp_pdma_config_write() local
701 return -EINVAL; in mmp_pdma_config_write()
704 chan->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC; in mmp_pdma_config_write()
705 maxburst = cfg->src_maxburst; in mmp_pdma_config_write()
706 width = cfg->src_addr_width; in mmp_pdma_config_write()
707 addr = cfg->src_addr; in mmp_pdma_config_write()
709 chan->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG; in mmp_pdma_config_write()
710 maxburst = cfg->dst_maxburst; in mmp_pdma_config_write()
711 width = cfg->dst_addr_width; in mmp_pdma_config_write()
712 addr = cfg->dst_addr; in mmp_pdma_config_write()
716 chan->dcmd |= DCMD_WIDTH1; in mmp_pdma_config_write()
718 chan->dcmd |= DCMD_WIDTH2; in mmp_pdma_config_write()
720 chan->dcmd |= DCMD_WIDTH4; in mmp_pdma_config_write()
722 if (maxburst == 8) in mmp_pdma_config_write()
723 chan->dcmd |= DCMD_BURST8; in mmp_pdma_config_write()
724 else if (maxburst == 16) in mmp_pdma_config_write()
725 chan->dcmd |= DCMD_BURST16; in mmp_pdma_config_write()
726 else if (maxburst == 32) in mmp_pdma_config_write()
727 chan->dcmd |= DCMD_BURST32; in mmp_pdma_config_write()
729 chan->dir = direction; in mmp_pdma_config_write()
730 chan->dev_addr = addr; in mmp_pdma_config_write()
735 if (cfg->slave_id) in mmp_pdma_config_write()
736 chan->drcmr = cfg->slave_id; in mmp_pdma_config_write()
746 memcpy(&chan->slave_config, cfg, sizeof(*cfg)); in mmp_pdma_config()
756 return -EINVAL; in mmp_pdma_terminate_all()
758 disable_chan(chan->phy); in mmp_pdma_terminate_all()
760 spin_lock_irqsave(&chan->desc_lock, flags); in mmp_pdma_terminate_all()
761 mmp_pdma_free_desc_list(chan, &chan->chain_pending); in mmp_pdma_terminate_all()
762 mmp_pdma_free_desc_list(chan, &chan->chain_running); in mmp_pdma_terminate_all()
763 spin_unlock_irqrestore(&chan->desc_lock, flags); in mmp_pdma_terminate_all()
764 chan->idle = true; in mmp_pdma_terminate_all()
775 bool cyclic = chan->cyclic_first != NULL; in mmp_pdma_residue()
781 if (!chan->phy) in mmp_pdma_residue()
784 if (chan->dir == DMA_DEV_TO_MEM) in mmp_pdma_residue()
785 curr = readl(chan->phy->base + DTADR(chan->phy->idx)); in mmp_pdma_residue()
787 curr = readl(chan->phy->base + DSADR(chan->phy->idx)); in mmp_pdma_residue()
789 list_for_each_entry(sw, &chan->chain_running, node) { in mmp_pdma_residue()
792 if (chan->dir == DMA_DEV_TO_MEM) in mmp_pdma_residue()
793 start = sw->desc.dtadr; in mmp_pdma_residue()
795 start = sw->desc.dsadr; in mmp_pdma_residue()
797 len = sw->desc.dcmd & DCMD_LENGTH; in mmp_pdma_residue()
811 residue += end - curr; in mmp_pdma_residue()
828 if (cyclic || !(sw->desc.dcmd & DCMD_ENDIRQEN)) in mmp_pdma_residue()
831 if (sw->async_tx.cookie == cookie) { in mmp_pdma_residue()
858 * mmp_pdma_issue_pending - Issue the DMA start command
866 spin_lock_irqsave(&chan->desc_lock, flags); in mmp_pdma_issue_pending()
868 spin_unlock_irqrestore(&chan->desc_lock, flags); in mmp_pdma_issue_pending()
884 if (chan->cyclic_first) { in dma_do_tasklet()
885 spin_lock_irqsave(&chan->desc_lock, flags); in dma_do_tasklet()
886 desc = chan->cyclic_first; in dma_do_tasklet()
887 dmaengine_desc_get_callback(&desc->async_tx, &cb); in dma_do_tasklet()
888 spin_unlock_irqrestore(&chan->desc_lock, flags); in dma_do_tasklet()
896 spin_lock_irqsave(&chan->desc_lock, flags); in dma_do_tasklet()
898 list_for_each_entry_safe(desc, _desc, &chan->chain_running, node) { in dma_do_tasklet()
903 list_move(&desc->node, &chain_cleanup); in dma_do_tasklet()
910 if (desc->desc.dcmd & DCMD_ENDIRQEN) { in dma_do_tasklet()
911 dma_cookie_t cookie = desc->async_tx.cookie; in dma_do_tasklet()
912 dma_cookie_complete(&desc->async_tx); in dma_do_tasklet()
913 dev_dbg(chan->dev, "completed_cookie=%d\n", cookie); in dma_do_tasklet()
922 chan->idle = list_empty(&chan->chain_running); in dma_do_tasklet()
926 spin_unlock_irqrestore(&chan->desc_lock, flags); in dma_do_tasklet()
930 struct dma_async_tx_descriptor *txd = &desc->async_tx; in dma_do_tasklet()
933 list_del(&desc->node); in dma_do_tasklet()
938 dma_pool_free(chan->desc_pool, desc, txd->phys); in dma_do_tasklet()
948 if (op->dev.of_node) in mmp_pdma_remove()
949 of_dma_controller_free(op->dev.of_node); in mmp_pdma_remove()
951 for (i = 0; i < pdev->dma_channels; i++) { in mmp_pdma_remove()
956 if (irq_num != pdev->dma_channels) { in mmp_pdma_remove()
958 devm_free_irq(&op->dev, irq, pdev); in mmp_pdma_remove()
960 for (i = 0; i < pdev->dma_channels; i++) { in mmp_pdma_remove()
961 phy = &pdev->phy[i]; in mmp_pdma_remove()
963 devm_free_irq(&op->dev, irq, phy); in mmp_pdma_remove()
967 dma_async_device_unregister(&pdev->device); in mmp_pdma_remove()
973 struct mmp_pdma_phy *phy = &pdev->phy[idx]; in mmp_pdma_chan_init()
977 chan = devm_kzalloc(pdev->dev, sizeof(*chan), GFP_KERNEL); in mmp_pdma_chan_init()
979 return -ENOMEM; in mmp_pdma_chan_init()
981 phy->idx = idx; in mmp_pdma_chan_init()
982 phy->base = pdev->base; in mmp_pdma_chan_init()
985 ret = devm_request_irq(pdev->dev, irq, mmp_pdma_chan_handler, in mmp_pdma_chan_init()
988 dev_err(pdev->dev, "channel request irq fail!\n"); in mmp_pdma_chan_init()
993 spin_lock_init(&chan->desc_lock); in mmp_pdma_chan_init()
994 chan->dev = pdev->dev; in mmp_pdma_chan_init()
995 chan->chan.device = &pdev->device; in mmp_pdma_chan_init()
996 tasklet_setup(&chan->tasklet, dma_do_tasklet); in mmp_pdma_chan_init()
997 INIT_LIST_HEAD(&chan->chain_pending); in mmp_pdma_chan_init()
998 INIT_LIST_HEAD(&chan->chain_running); in mmp_pdma_chan_init()
1000 /* register virt channel to dma engine */ in mmp_pdma_chan_init()
1001 list_add_tail(&chan->chan.device_node, &pdev->device.channels); in mmp_pdma_chan_init()
1007 { .compatible = "marvell,pdma-1.0", },
1015 struct mmp_pdma_device *d = ofdma->of_dma_data; in mmp_pdma_dma_xlate()
1018 chan = dma_get_any_slave_channel(&d->device); in mmp_pdma_dma_xlate()
1022 to_mmp_pdma_chan(chan)->drcmr = dma_spec->args[0]; in mmp_pdma_dma_xlate()
1031 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev); in mmp_pdma_probe()
1039 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL); in mmp_pdma_probe()
1041 return -ENOMEM; in mmp_pdma_probe()
1043 pdev->dev = &op->dev; in mmp_pdma_probe()
1045 spin_lock_init(&pdev->phy_lock); in mmp_pdma_probe()
1048 pdev->base = devm_ioremap_resource(pdev->dev, iores); in mmp_pdma_probe()
1049 if (IS_ERR(pdev->base)) in mmp_pdma_probe()
1050 return PTR_ERR(pdev->base); in mmp_pdma_probe()
1052 of_id = of_match_device(mmp_pdma_dt_ids, pdev->dev); in mmp_pdma_probe()
1054 of_property_read_u32(pdev->dev->of_node, "#dma-channels", in mmp_pdma_probe()
1056 else if (pdata && pdata->dma_channels) in mmp_pdma_probe()
1057 dma_channels = pdata->dma_channels; in mmp_pdma_probe()
1060 pdev->dma_channels = dma_channels; in mmp_pdma_probe()
1067 pdev->phy = devm_kcalloc(pdev->dev, dma_channels, sizeof(*pdev->phy), in mmp_pdma_probe()
1069 if (pdev->phy == NULL) in mmp_pdma_probe()
1070 return -ENOMEM; in mmp_pdma_probe()
1072 INIT_LIST_HEAD(&pdev->device.channels); in mmp_pdma_probe()
1077 ret = devm_request_irq(pdev->dev, irq, mmp_pdma_int_handler, in mmp_pdma_probe()
1090 dma_cap_set(DMA_SLAVE, pdev->device.cap_mask); in mmp_pdma_probe()
1091 dma_cap_set(DMA_MEMCPY, pdev->device.cap_mask); in mmp_pdma_probe()
1092 dma_cap_set(DMA_CYCLIC, pdev->device.cap_mask); in mmp_pdma_probe()
1093 dma_cap_set(DMA_PRIVATE, pdev->device.cap_mask); in mmp_pdma_probe()
1094 pdev->device.dev = &op->dev; in mmp_pdma_probe()
1095 pdev->device.device_alloc_chan_resources = mmp_pdma_alloc_chan_resources; in mmp_pdma_probe()
1096 pdev->device.device_free_chan_resources = mmp_pdma_free_chan_resources; in mmp_pdma_probe()
1097 pdev->device.device_tx_status = mmp_pdma_tx_status; in mmp_pdma_probe()
1098 pdev->device.device_prep_dma_memcpy = mmp_pdma_prep_memcpy; in mmp_pdma_probe()
1099 pdev->device.device_prep_slave_sg = mmp_pdma_prep_slave_sg; in mmp_pdma_probe()
1100 pdev->device.device_prep_dma_cyclic = mmp_pdma_prep_dma_cyclic; in mmp_pdma_probe()
1101 pdev->device.device_issue_pending = mmp_pdma_issue_pending; in mmp_pdma_probe()
1102 pdev->device.device_config = mmp_pdma_config; in mmp_pdma_probe()
1103 pdev->device.device_terminate_all = mmp_pdma_terminate_all; in mmp_pdma_probe()
1104 pdev->device.copy_align = DMAENGINE_ALIGN_8_BYTES; in mmp_pdma_probe()
1105 pdev->device.src_addr_widths = widths; in mmp_pdma_probe()
1106 pdev->device.dst_addr_widths = widths; in mmp_pdma_probe()
1107 pdev->device.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); in mmp_pdma_probe()
1108 pdev->device.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; in mmp_pdma_probe()
1110 if (pdev->dev->coherent_dma_mask) in mmp_pdma_probe()
1111 dma_set_mask(pdev->dev, pdev->dev->coherent_dma_mask); in mmp_pdma_probe()
1113 dma_set_mask(pdev->dev, DMA_BIT_MASK(64)); in mmp_pdma_probe()
1115 ret = dma_async_device_register(&pdev->device); in mmp_pdma_probe()
1117 dev_err(pdev->device.dev, "unable to register\n"); in mmp_pdma_probe()
1121 if (op->dev.of_node) { in mmp_pdma_probe()
1122 /* Device-tree DMA controller registration */ in mmp_pdma_probe()
1123 ret = of_dma_controller_register(op->dev.of_node, in mmp_pdma_probe()
1126 dev_err(&op->dev, "of_dma_controller_register failed\n"); in mmp_pdma_probe()
1132 dev_info(pdev->device.dev, "initialized %d channels\n", dma_channels); in mmp_pdma_probe()
1137 { "mmp-pdma", },
1143 .name = "mmp-pdma",
1155 if (chan->device->dev->driver != &mmp_pdma_driver.driver) in mmp_pdma_filter_fn()
1158 c->drcmr = *(unsigned int *)param; in mmp_pdma_filter_fn()
1166 MODULE_DESCRIPTION("MARVELL MMP Peripheral DMA Driver");