Lines Matching +full:dma +full:- +full:channel +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0
3 * Core driver for the Synopsys DesignWare DMA Controller
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
13 #include <linux/dma-mapping.h>
28 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
37 /* The set of bus widths supported by the DMA controller */
44 /*----------------------------------------------------------------------*/
48 return &chan->dev->device; in chan2dev()
53 return to_dw_desc(dwc->active_list.next); in dwc_first_active()
59 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); in dwc_tx_submit()
63 spin_lock_irqsave(&dwc->lock, flags); in dwc_tx_submit()
69 * for DMA. But this is hard to do in a race-free manner. in dwc_tx_submit()
72 list_add_tail(&desc->desc_node, &dwc->queue); in dwc_tx_submit()
73 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_tx_submit()
74 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", in dwc_tx_submit()
75 __func__, desc->txd.cookie); in dwc_tx_submit()
82 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_get()
86 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); in dwc_desc_get()
90 dwc->descs_allocated++; in dwc_desc_get()
91 INIT_LIST_HEAD(&desc->tx_list); in dwc_desc_get()
92 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); in dwc_desc_get()
93 desc->txd.tx_submit = dwc_tx_submit; in dwc_desc_get()
94 desc->txd.flags = DMA_CTRL_ACK; in dwc_desc_get()
95 desc->txd.phys = phys; in dwc_desc_get()
101 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_put()
107 list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) { in dwc_desc_put()
108 list_del(&child->desc_node); in dwc_desc_put()
109 dma_pool_free(dw->desc_pool, child, child->txd.phys); in dwc_desc_put()
110 dwc->descs_allocated--; in dwc_desc_put()
113 dma_pool_free(dw->desc_pool, desc, desc->txd.phys); in dwc_desc_put()
114 dwc->descs_allocated--; in dwc_desc_put()
119 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_initialize()
121 dw->initialize_chan(dwc); in dwc_initialize()
124 channel_set_bit(dw, MASK.XFER, dwc->mask); in dwc_initialize()
125 channel_set_bit(dw, MASK.ERROR, dwc->mask); in dwc_initialize()
128 /*----------------------------------------------------------------------*/
132 dev_err(chan2dev(&dwc->chan), in dwc_dump_chan_regs()
143 channel_clear_bit(dw, CH_EN, dwc->mask); in dwc_chan_disable()
144 while (dma_readl(dw, CH_EN) & dwc->mask) in dwc_chan_disable()
148 /*----------------------------------------------------------------------*/
154 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_do_single_block()
167 channel_set_bit(dw, CH_EN, dwc->mask); in dwc_do_single_block()
170 dwc->tx_node_active = dwc->tx_node_active->next; in dwc_do_single_block()
173 /* Called with dwc->lock held and bh disabled */
176 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_dostart()
177 u8 lms = DWC_LLP_LMS(dwc->dws.m_master); in dwc_dostart()
180 /* ASSERT: channel is idle */ in dwc_dostart()
181 if (dma_readl(dw, CH_EN) & dwc->mask) { in dwc_dostart()
182 dev_err(chan2dev(&dwc->chan), in dwc_dostart()
183 "%s: BUG: Attempted to start non-idle channel\n", in dwc_dostart()
191 if (dwc->nollp) { in dwc_dostart()
193 &dwc->flags); in dwc_dostart()
195 dev_err(chan2dev(&dwc->chan), in dwc_dostart()
202 first->residue = first->total_len; in dwc_dostart()
203 dwc->tx_node_active = &first->tx_list; in dwc_dostart()
213 channel_writel(dwc, LLP, first->txd.phys | lms); in dwc_dostart()
216 channel_set_bit(dw, CH_EN, dwc->mask); in dwc_dostart()
223 if (list_empty(&dwc->queue)) in dwc_dostart_first_queued()
226 list_move(dwc->queue.next, &dwc->active_list); in dwc_dostart_first_queued()
228 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); in dwc_dostart_first_queued()
232 /*----------------------------------------------------------------------*/
238 struct dma_async_tx_descriptor *txd = &desc->txd; in dwc_descriptor_complete()
243 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); in dwc_descriptor_complete()
245 spin_lock_irqsave(&dwc->lock, flags); in dwc_descriptor_complete()
253 list_for_each_entry(child, &desc->tx_list, desc_node) in dwc_descriptor_complete()
254 async_tx_ack(&child->txd); in dwc_descriptor_complete()
255 async_tx_ack(&desc->txd); in dwc_descriptor_complete()
257 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_descriptor_complete()
268 spin_lock_irqsave(&dwc->lock, flags); in dwc_complete_all()
269 if (dma_readl(dw, CH_EN) & dwc->mask) { in dwc_complete_all()
270 dev_err(chan2dev(&dwc->chan), in dwc_complete_all()
271 "BUG: XFER bit set, but channel not idle!\n"); in dwc_complete_all()
273 /* Try to continue after resetting the channel... */ in dwc_complete_all()
281 list_splice_init(&dwc->active_list, &list); in dwc_complete_all()
284 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_complete_all()
293 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_get_sent()
297 return dw->block2bytes(dwc, ctlhi, ctllo >> 4 & 7); in dwc_get_sent()
308 spin_lock_irqsave(&dwc->lock, flags); in dwc_scan_descriptors()
312 if (status_xfer & dwc->mask) { in dwc_scan_descriptors()
314 dma_writel(dw, CLEAR.XFER, dwc->mask); in dwc_scan_descriptors()
316 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { in dwc_scan_descriptors()
317 struct list_head *head, *active = dwc->tx_node_active; in dwc_scan_descriptors()
325 head = &desc->tx_list; in dwc_scan_descriptors()
328 if (active == head->next) in dwc_scan_descriptors()
329 desc->residue -= desc->len; in dwc_scan_descriptors()
331 desc->residue -= to_dw_desc(active->prev)->len; in dwc_scan_descriptors()
338 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
343 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); in dwc_scan_descriptors()
346 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
352 if (list_empty(&dwc->active_list)) { in dwc_scan_descriptors()
353 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
357 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { in dwc_scan_descriptors()
358 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); in dwc_scan_descriptors()
359 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
363 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); in dwc_scan_descriptors()
365 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { in dwc_scan_descriptors()
367 desc->residue = desc->total_len; in dwc_scan_descriptors()
370 if (desc->txd.phys == DWC_LLP_LOC(llp)) { in dwc_scan_descriptors()
371 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
378 desc->residue -= dwc_get_sent(dwc); in dwc_scan_descriptors()
379 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
383 desc->residue -= desc->len; in dwc_scan_descriptors()
384 list_for_each_entry(child, &desc->tx_list, desc_node) { in dwc_scan_descriptors()
387 desc->residue -= dwc_get_sent(dwc); in dwc_scan_descriptors()
388 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
391 desc->residue -= child->len; in dwc_scan_descriptors()
398 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
400 spin_lock_irqsave(&dwc->lock, flags); in dwc_scan_descriptors()
403 dev_err(chan2dev(&dwc->chan), in dwc_scan_descriptors()
404 "BUG: All descriptors done, but channel not idle!\n"); in dwc_scan_descriptors()
406 /* Try to continue after resetting the channel... */ in dwc_scan_descriptors()
410 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
415 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", in dwc_dump_lli()
431 spin_lock_irqsave(&dwc->lock, flags); in dwc_handle_error()
439 list_del_init(&bad_desc->desc_node); in dwc_handle_error()
440 list_move(dwc->queue.next, dwc->active_list.prev); in dwc_handle_error()
443 dma_writel(dw, CLEAR.ERROR, dwc->mask); in dwc_handle_error()
444 if (!list_empty(&dwc->active_list)) in dwc_handle_error()
454 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" in dwc_handle_error()
455 " cookie: %d\n", bad_desc->txd.cookie); in dwc_handle_error()
457 list_for_each_entry(child, &bad_desc->tx_list, desc_node) in dwc_handle_error()
460 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_handle_error()
477 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); in dw_dma_tasklet()
479 for (i = 0; i < dw->dma.chancnt; i++) { in dw_dma_tasklet()
480 dwc = &dw->chan[i]; in dw_dma_tasklet()
481 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) in dw_dma_tasklet()
482 dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n"); in dw_dma_tasklet()
489 /* Re-enable interrupts */ in dw_dma_tasklet()
490 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_tasklet()
491 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_tasklet()
500 if (!dw->in_use) in dw_dma_interrupt()
504 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); in dw_dma_interrupt()
514 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_interrupt()
515 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); in dw_dma_interrupt()
516 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_interrupt()
520 dev_err(dw->dma.dev, in dw_dma_interrupt()
525 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); in dw_dma_interrupt()
526 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); in dw_dma_interrupt()
527 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); in dw_dma_interrupt()
528 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); in dw_dma_interrupt()
529 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); in dw_dma_interrupt()
532 tasklet_schedule(&dw->tasklet); in dw_dma_interrupt()
537 /*----------------------------------------------------------------------*/
544 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_prep_dma_memcpy()
550 u8 m_master = dwc->dws.m_master; in dwc_prep_dma_memcpy()
553 unsigned int data_width = dw->pdata->data_width[m_master]; in dwc_prep_dma_memcpy()
566 dwc->direction = DMA_MEM_TO_MEM; in dwc_prep_dma_memcpy()
570 ctllo = dw->prepare_ctllo(dwc) in dwc_prep_dma_memcpy()
583 ctlhi = dw->bytes2block(dwc, len - offset, src_width, &xfer_count); in dwc_prep_dma_memcpy()
589 desc->len = xfer_count; in dwc_prep_dma_memcpy()
594 lli_write(prev, llp, desc->txd.phys | lms); in dwc_prep_dma_memcpy()
595 list_add_tail(&desc->desc_node, &first->tx_list); in dwc_prep_dma_memcpy()
604 prev->lli.llp = 0; in dwc_prep_dma_memcpy()
606 first->txd.flags = flags; in dwc_prep_dma_memcpy()
607 first->total_len = len; in dwc_prep_dma_memcpy()
609 return &first->txd; in dwc_prep_dma_memcpy()
622 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_prep_slave_sg()
623 struct dma_slave_config *sconfig = &dwc->dma_sconfig; in dwc_prep_slave_sg()
627 u8 m_master = dwc->dws.m_master; in dwc_prep_slave_sg()
632 unsigned int data_width = dw->pdata->data_width[m_master]; in dwc_prep_slave_sg()
642 dwc->direction = direction; in dwc_prep_slave_sg()
648 reg_width = __ffs(sconfig->dst_addr_width); in dwc_prep_slave_sg()
649 reg = sconfig->dst_addr; in dwc_prep_slave_sg()
650 ctllo = dw->prepare_ctllo(dwc) in dwc_prep_slave_sg()
655 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : in dwc_prep_slave_sg()
673 ctlhi = dw->bytes2block(dwc, len, mem_width, &dlen); in dwc_prep_slave_sg()
679 desc->len = dlen; in dwc_prep_slave_sg()
684 lli_write(prev, llp, desc->txd.phys | lms); in dwc_prep_slave_sg()
685 list_add_tail(&desc->desc_node, &first->tx_list); in dwc_prep_slave_sg()
690 len -= dlen; in dwc_prep_slave_sg()
698 reg_width = __ffs(sconfig->src_addr_width); in dwc_prep_slave_sg()
699 reg = sconfig->src_addr; in dwc_prep_slave_sg()
700 ctllo = dw->prepare_ctllo(dwc) in dwc_prep_slave_sg()
705 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : in dwc_prep_slave_sg()
721 ctlhi = dw->bytes2block(dwc, len, reg_width, &dlen); in dwc_prep_slave_sg()
728 desc->len = dlen; in dwc_prep_slave_sg()
733 lli_write(prev, llp, desc->txd.phys | lms); in dwc_prep_slave_sg()
734 list_add_tail(&desc->desc_node, &first->tx_list); in dwc_prep_slave_sg()
739 len -= dlen; in dwc_prep_slave_sg()
754 prev->lli.llp = 0; in dwc_prep_slave_sg()
756 first->total_len = total_len; in dwc_prep_slave_sg()
758 return &first->txd; in dwc_prep_slave_sg()
772 if (dws->dma_dev != chan->device->dev) in dw_dma_filter()
775 /* permit channels in accordance with the channels mask */ in dw_dma_filter()
776 if (dws->channels && !(dws->channels & dwc->mask)) in dw_dma_filter()
780 memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave)); in dw_dma_filter()
789 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_config()
791 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); in dwc_config()
793 dwc->dma_sconfig.src_maxburst = in dwc_config()
794 clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst); in dwc_config()
795 dwc->dma_sconfig.dst_maxburst = in dwc_config()
796 clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst); in dwc_config()
798 dw->encode_maxburst(dwc, &dwc->dma_sconfig.src_maxburst); in dwc_config()
799 dw->encode_maxburst(dwc, &dwc->dma_sconfig.dst_maxburst); in dwc_config()
806 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_chan_pause()
809 dw->suspend_chan(dwc, drain); in dwc_chan_pause()
811 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) in dwc_chan_pause()
814 set_bit(DW_DMA_IS_PAUSED, &dwc->flags); in dwc_chan_pause()
822 spin_lock_irqsave(&dwc->lock, flags); in dwc_pause()
824 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_pause()
831 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_chan_resume()
833 dw->resume_chan(dwc, drain); in dwc_chan_resume()
835 clear_bit(DW_DMA_IS_PAUSED, &dwc->flags); in dwc_chan_resume()
843 spin_lock_irqsave(&dwc->lock, flags); in dwc_resume()
845 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) in dwc_resume()
848 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_resume()
856 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_terminate_all()
861 spin_lock_irqsave(&dwc->lock, flags); in dwc_terminate_all()
863 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); in dwc_terminate_all()
872 list_splice_init(&dwc->queue, &list); in dwc_terminate_all()
873 list_splice_init(&dwc->active_list, &list); in dwc_terminate_all()
875 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_terminate_all()
888 list_for_each_entry(desc, &dwc->active_list, desc_node) in dwc_find_desc()
889 if (desc->txd.cookie == c) in dwc_find_desc()
901 spin_lock_irqsave(&dwc->lock, flags); in dwc_get_residue()
906 residue = desc->residue; in dwc_get_residue()
907 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) in dwc_get_residue()
908 residue -= dwc_get_sent(dwc); in dwc_get_residue()
910 residue = desc->total_len; in dwc_get_residue()
916 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_get_residue()
932 dwc_scan_descriptors(to_dw_dma(chan->device), dwc); in dwc_tx_status()
940 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS) in dwc_tx_status()
951 spin_lock_irqsave(&dwc->lock, flags); in dwc_issue_pending()
952 if (list_empty(&dwc->active_list)) in dwc_issue_pending()
954 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_issue_pending()
957 /*----------------------------------------------------------------------*/
963 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); in do_dw_dma_off()
964 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); in do_dw_dma_off()
965 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); in do_dw_dma_off()
966 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); in do_dw_dma_off()
967 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); in do_dw_dma_off()
981 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_alloc_chan_resources()
985 /* ASSERT: channel is idle */ in dwc_alloc_chan_resources()
986 if (dma_readl(dw, CH_EN) & dwc->mask) { in dwc_alloc_chan_resources()
987 dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); in dwc_alloc_chan_resources()
988 return -EIO; in dwc_alloc_chan_resources()
995 * need to initialize here, like "scatter-gather" (which in dwc_alloc_chan_resources()
1000 * We need controller-specific data to set up slave transfers. in dwc_alloc_chan_resources()
1002 if (chan->private && !dw_dma_filter(chan, chan->private)) { in dwc_alloc_chan_resources()
1003 dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); in dwc_alloc_chan_resources()
1004 return -EINVAL; in dwc_alloc_chan_resources()
1008 if (!dw->in_use) in dwc_alloc_chan_resources()
1010 dw->in_use |= dwc->mask; in dwc_alloc_chan_resources()
1018 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_free_chan_resources()
1022 dwc->descs_allocated); in dwc_free_chan_resources()
1024 /* ASSERT: channel is idle */ in dwc_free_chan_resources()
1025 BUG_ON(!list_empty(&dwc->active_list)); in dwc_free_chan_resources()
1026 BUG_ON(!list_empty(&dwc->queue)); in dwc_free_chan_resources()
1027 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); in dwc_free_chan_resources()
1029 spin_lock_irqsave(&dwc->lock, flags); in dwc_free_chan_resources()
1031 /* Clear custom channel configuration */ in dwc_free_chan_resources()
1032 memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); in dwc_free_chan_resources()
1035 channel_clear_bit(dw, MASK.XFER, dwc->mask); in dwc_free_chan_resources()
1036 channel_clear_bit(dw, MASK.BLOCK, dwc->mask); in dwc_free_chan_resources()
1037 channel_clear_bit(dw, MASK.ERROR, dwc->mask); in dwc_free_chan_resources()
1039 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_free_chan_resources()
1042 dw->in_use &= ~dwc->mask; in dwc_free_chan_resources()
1043 if (!dw->in_use) in dwc_free_chan_resources()
1053 caps->max_burst = dwc->max_burst; in dwc_caps()
1057 * accelerated multi-block transfers supported, aka LLPs in DW DMAC in dwc_caps()
1060 * single DMA transaction, otherwise it's just one SG entry. in dwc_caps()
1062 if (dwc->nollp) in dwc_caps()
1063 caps->max_sg_burst = 1; in dwc_caps()
1065 caps->max_sg_burst = 0; in dwc_caps()
1070 struct dw_dma *dw = chip->dw; in do_dma_probe()
1077 dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL); in do_dma_probe()
1078 if (!dw->pdata) in do_dma_probe()
1079 return -ENOMEM; in do_dma_probe()
1081 dw->regs = chip->regs; in do_dma_probe()
1083 pm_runtime_get_sync(chip->dev); in do_dma_probe()
1085 if (!chip->pdata) { in do_dma_probe()
1087 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); in do_dma_probe()
1091 err = -EINVAL; in do_dma_probe()
1096 pdata = dw->pdata; in do_dma_probe()
1099 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; in do_dma_probe()
1100 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; in do_dma_probe()
1101 for (i = 0; i < pdata->nr_masters; i++) { in do_dma_probe()
1102 pdata->data_width[i] = in do_dma_probe()
1105 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE); in do_dma_probe()
1108 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; in do_dma_probe()
1109 pdata->chan_priority = CHAN_PRIORITY_ASCENDING; in do_dma_probe()
1110 } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { in do_dma_probe()
1111 err = -EINVAL; in do_dma_probe()
1114 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata)); in do_dma_probe()
1117 pdata = dw->pdata; in do_dma_probe()
1120 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), in do_dma_probe()
1122 if (!dw->chan) { in do_dma_probe()
1123 err = -ENOMEM; in do_dma_probe()
1127 /* Calculate all channel mask before DMA setup */ in do_dma_probe()
1128 dw->all_chan_mask = (1 << pdata->nr_channels) - 1; in do_dma_probe()
1130 /* Force dma off, just in case */ in do_dma_probe()
1131 dw->disable(dw); in do_dma_probe()
1133 /* Device and instance ID for IRQ and DMA pool */ in do_dma_probe()
1134 dw->set_device_name(dw, chip->id); in do_dma_probe()
1137 dw->desc_pool = dmam_pool_create(dw->name, chip->dev, in do_dma_probe()
1139 if (!dw->desc_pool) { in do_dma_probe()
1140 dev_err(chip->dev, "No memory for descriptors dma pool\n"); in do_dma_probe()
1141 err = -ENOMEM; in do_dma_probe()
1145 tasklet_setup(&dw->tasklet, dw_dma_tasklet); in do_dma_probe()
1147 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, in do_dma_probe()
1148 dw->name, dw); in do_dma_probe()
1152 INIT_LIST_HEAD(&dw->dma.channels); in do_dma_probe()
1153 for (i = 0; i < pdata->nr_channels; i++) { in do_dma_probe()
1154 struct dw_dma_chan *dwc = &dw->chan[i]; in do_dma_probe()
1156 dwc->chan.device = &dw->dma; in do_dma_probe()
1157 dma_cookie_init(&dwc->chan); in do_dma_probe()
1158 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) in do_dma_probe()
1159 list_add_tail(&dwc->chan.device_node, in do_dma_probe()
1160 &dw->dma.channels); in do_dma_probe()
1162 list_add(&dwc->chan.device_node, &dw->dma.channels); in do_dma_probe()
1165 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) in do_dma_probe()
1166 dwc->priority = pdata->nr_channels - i - 1; in do_dma_probe()
1168 dwc->priority = i; in do_dma_probe()
1170 dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; in do_dma_probe()
1171 spin_lock_init(&dwc->lock); in do_dma_probe()
1172 dwc->mask = 1 << i; in do_dma_probe()
1174 INIT_LIST_HEAD(&dwc->active_list); in do_dma_probe()
1175 INIT_LIST_HEAD(&dwc->queue); in do_dma_probe()
1177 channel_clear_bit(dw, CH_EN, dwc->mask); in do_dma_probe()
1179 dwc->direction = DMA_TRANS_NONE; in do_dma_probe()
1183 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; in do_dma_probe()
1184 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; in do_dma_probe()
1187 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, in do_dma_probe()
1191 * Decode maximum block size for given channel. The in do_dma_probe()
1195 dwc->block_size = in do_dma_probe()
1196 (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; in do_dma_probe()
1199 * According to the DW DMA databook the true scatter- in do_dma_probe()
1200 * gether LLPs aren't available if either multi-block in do_dma_probe()
1202 * LLP register is hard-coded to zeros in do_dma_probe()
1205 dwc->nollp = in do_dma_probe()
1208 dwc->max_burst = in do_dma_probe()
1211 dwc->block_size = pdata->block_size; in do_dma_probe()
1212 dwc->nollp = !pdata->multi_block[i]; in do_dma_probe()
1213 dwc->max_burst = pdata->max_burst[i] ?: DW_DMA_MAX_BURST; in do_dma_probe()
1218 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); in do_dma_probe()
1219 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); in do_dma_probe()
1220 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); in do_dma_probe()
1221 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); in do_dma_probe()
1222 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); in do_dma_probe()
1225 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); in do_dma_probe()
1226 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); in do_dma_probe()
1227 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); in do_dma_probe()
1229 dw->dma.dev = chip->dev; in do_dma_probe()
1230 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; in do_dma_probe()
1231 dw->dma.device_free_chan_resources = dwc_free_chan_resources; in do_dma_probe()
1233 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; in do_dma_probe()
1234 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; in do_dma_probe()
1236 dw->dma.device_caps = dwc_caps; in do_dma_probe()
1237 dw->dma.device_config = dwc_config; in do_dma_probe()
1238 dw->dma.device_pause = dwc_pause; in do_dma_probe()
1239 dw->dma.device_resume = dwc_resume; in do_dma_probe()
1240 dw->dma.device_terminate_all = dwc_terminate_all; in do_dma_probe()
1242 dw->dma.device_tx_status = dwc_tx_status; in do_dma_probe()
1243 dw->dma.device_issue_pending = dwc_issue_pending; in do_dma_probe()
1245 /* DMA capabilities */ in do_dma_probe()
1246 dw->dma.min_burst = DW_DMA_MIN_BURST; in do_dma_probe()
1247 dw->dma.max_burst = DW_DMA_MAX_BURST; in do_dma_probe()
1248 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; in do_dma_probe()
1249 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; in do_dma_probe()
1250 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | in do_dma_probe()
1252 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in do_dma_probe()
1257 * size as the block size found for the very first channel. in do_dma_probe()
1259 dma_set_max_seg_size(dw->dma.dev, dw->chan[0].block_size); in do_dma_probe()
1261 err = dma_async_device_register(&dw->dma); in do_dma_probe()
1265 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", in do_dma_probe()
1266 pdata->nr_channels); in do_dma_probe()
1268 pm_runtime_put_sync_suspend(chip->dev); in do_dma_probe()
1273 free_irq(chip->irq, dw); in do_dma_probe()
1275 pm_runtime_put_sync_suspend(chip->dev); in do_dma_probe()
1281 struct dw_dma *dw = chip->dw; in do_dma_remove()
1284 pm_runtime_get_sync(chip->dev); in do_dma_remove()
1287 dma_async_device_unregister(&dw->dma); in do_dma_remove()
1289 free_irq(chip->irq, dw); in do_dma_remove()
1290 tasklet_kill(&dw->tasklet); in do_dma_remove()
1292 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, in do_dma_remove()
1294 list_del(&dwc->chan.device_node); in do_dma_remove()
1295 channel_clear_bit(dw, CH_EN, dwc->mask); in do_dma_remove()
1298 pm_runtime_put_sync_suspend(chip->dev); in do_dma_remove()
1304 struct dw_dma *dw = chip->dw; in do_dw_dma_disable()
1306 dw->disable(dw); in do_dw_dma_disable()
1313 struct dw_dma *dw = chip->dw; in do_dw_dma_enable()
1315 dw->enable(dw); in do_dw_dma_enable()
1321 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");