Lines Matching +full:0 +full:x100008
21 #define QM_VF_AEQ_INT_SOURCE 0x0
22 #define QM_VF_AEQ_INT_MASK 0x4
23 #define QM_VF_EQ_INT_SOURCE 0x8
24 #define QM_VF_EQ_INT_MASK 0xc
29 #define QM_EQ_EVENT_IRQ_VECTOR 0
34 #define QM_MB_CMD_SQC 0x0
35 #define QM_MB_CMD_CQC 0x1
36 #define QM_MB_CMD_EQC 0x2
37 #define QM_MB_CMD_AEQC 0x3
38 #define QM_MB_CMD_SQC_BT 0x4
39 #define QM_MB_CMD_CQC_BT 0x5
40 #define QM_MB_CMD_SQC_VFT_V2 0x6
42 #define QM_MB_CMD_SEND_BASE 0x300
46 #define QM_MB_CMD_DATA_ADDR_L 0x304
47 #define QM_MB_CMD_DATA_ADDR_H 0x308
50 #define QM_SQ_HOP_NUM_SHIFT 0
54 #define QM_SQ_PRIORITY_SHIFT 0
58 #define QM_SQ_TYPE_MASK GENMASK(3, 0)
59 #define QM_SQ_TAIL_IDX(sqc) ((le16_to_cpu((sqc)->w11) >> 6) & 0x1)
62 #define QM_CQ_HOP_NUM_SHIFT 0
66 #define QM_CQ_PHASE_SHIFT 0
69 #define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1)
71 #define QM_CQ_TAIL_IDX(cqc) ((le16_to_cpu((cqc)->w11) >> 6) & 0x1)
77 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
78 #define QM_EQE_CQN_MASK GENMASK(15, 0)
80 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
83 #define QM_DOORBELL_CMD_SQ 0
88 #define QM_DOORBELL_BASE_V1 0x340
92 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
93 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
99 #define QM_MEM_START_INIT 0x100040
100 #define QM_MEM_INIT_DONE 0x100044
101 #define QM_VFT_CFG_RDY 0x10006c
102 #define QM_VFT_CFG_OP_WR 0x100058
103 #define QM_VFT_CFG_TYPE 0x10005c
104 #define QM_SQC_VFT 0x0
105 #define QM_CQC_VFT 0x1
106 #define QM_VFT_CFG 0x100060
107 #define QM_VFT_CFG_OP_ENABLE 0x100054
109 #define QM_VFT_CFG_DATA_L 0x100064
110 #define QM_VFT_CFG_DATA_H 0x100068
123 #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(5, 0)
125 #define QM_SQC_VFT_NUM_MASK_v2 GENMASK(9, 0)
127 #define QM_DFX_CNT_CLR_CE 0x100118
129 #define QM_ABNORMAL_INT_SOURCE 0x100000
130 #define QM_ABNORMAL_INT_SOURCE_CLR GENMASK(12, 0)
131 #define QM_ABNORMAL_INT_MASK 0x100004
132 #define QM_ABNORMAL_INT_MASK_VALUE 0x1fff
133 #define QM_ABNORMAL_INT_STATUS 0x100008
134 #define QM_ABNORMAL_INT_SET 0x10000c
135 #define QM_ABNORMAL_INF00 0x100010
136 #define QM_FIFO_OVERFLOW_TYPE 0xc0
138 #define QM_FIFO_OVERFLOW_VF 0x3f
139 #define QM_ABNORMAL_INF01 0x100014
140 #define QM_DB_TIMEOUT_TYPE 0xc0
142 #define QM_DB_TIMEOUT_VF 0x3f
143 #define QM_RAS_CE_ENABLE 0x1000ec
144 #define QM_RAS_FE_ENABLE 0x1000f0
145 #define QM_RAS_NFE_ENABLE 0x1000f4
146 #define QM_RAS_CE_THRESHOLD 0x1000f8
148 #define QM_RAS_MSI_INT_SEL 0x1040f4
150 #define QM_DEV_RESET_FLAG 0
152 #define QM_PEH_VENDOR_ID 0x1000d8
153 #define ACC_VENDOR_ID_VALUE 0x5a5a
154 #define QM_PEH_DFX_INFO0 0x1000fc
156 #define ACC_PEH_MSI_DISABLE GENMASK(31, 0)
157 #define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
159 #define ACC_MASTER_TRANS_RETURN 0x300150
160 #define ACC_MASTER_GLOBAL_CTRL 0x300000
161 #define ACC_AM_CFG_PORT_WR_EN 0x30001c
163 #define ACC_AM_ROB_ECC_INT_STS 0x300104
171 #define QM_CACHE_WB_START 0x204
172 #define QM_CACHE_WB_DONE 0x208
175 #define QM_SQE_DATA_ALIGN_MASK GENMASK(6, 0)
181 #define QM_PCI_COMMAND_INVALID ~0
185 #define QM_SQE_ADDR_MASK GENMASK(7, 0)
212 (qc)->head = 0; \
213 (qc)->tail = 0; \
216 (qc)->dw3 = 0; \
217 (qc)->w8 = 0; \
218 (qc)->rsvd0 = 0; \
220 (qc)->w11 = 0; \
221 (qc)->rsvd1 = 0; \
222 } while (0)
225 SQC_VFT = 0,
358 { .int_msk = BIT(0), .msg = "qm_axi_rresp" },
426 enum qp_state qp_curr = 0; in qm_qp_avail_state()
469 /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
476 0x1), 10, 1000); in qm_wait_mb_ready()
483 unsigned long tmp0 = 0, tmp1 = 0; in qm_mb_write()
491 asm volatile("ldp %0, %1, %3\n" in qm_mb_write()
492 "stp %0, %1, %2\n" in qm_mb_write()
505 int ret = 0; in qm_mb()
511 (op ? 0x1 << QM_MB_OP_SHIFT : 0) | in qm_mb()
512 (0x1 << QM_MB_BUSY_SHIFT)); in qm_mb()
516 mailbox.rsvd = 0; in qm_mb()
557 u16 randata = 0; in qm_db_v2()
584 writel(0x1, qm->io_base + QM_MEM_START_INIT); in qm_dev_mem_reset()
586 val & BIT(0), 10, 1000); in qm_dev_mem_reset()
613 qp->qp_status.cq_head = 0; in qm_cq_head_update()
636 qp->qp_status.cq_head, 0); in qm_poll_qp()
651 int eqe_num = 0; in qm_work_process()
661 qm->status.eq_head = 0; in qm_work_process()
668 eqe_num = 0; in qm_work_process()
669 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_work_process()
673 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_work_process()
698 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_irq()
725 qm->status.aeq_head = 0; in qm_aeq_irq()
731 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0); in qm_aeq_irq()
757 qp_status->sq_tail = 0; in qm_init_qp_status()
758 qp_status->cq_head = 0; in qm_init_qp_status()
760 atomic_set(&qp_status->used, 0); in qm_init_qp_status()
766 u64 tmp = 0; in qm_vft_data_cfg()
768 if (number > 0) { in qm_vft_data_cfg()
807 val & BIT(0), 10, 1000); in qm_set_vft_common()
811 writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR); in qm_set_vft_common()
817 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); in qm_set_vft_common()
818 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); in qm_set_vft_common()
821 val & BIT(0), 10, 1000); in qm_set_vft_common()
836 return 0; in qm_set_sqc_cqc_vft()
844 ret = qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1); in qm_get_vft_v2()
854 return 0; in qm_get_vft_v2()
887 return 0; in current_q_write()
897 /* rd_clr_ctrl 1 enable read clear, otherwise 0 disable it */
907 return 0; in clear_enable_write()
945 if (*pos != 0) in qm_debug_write()
946 return 0; in qm_debug_write()
953 if (len < 0) in qm_debug_write()
956 tbuf[len] = '\0'; in qm_debug_write()
957 if (kstrtoul(tbuf, 0, &val)) in qm_debug_write()
1000 {"QM_ECC_1BIT_CNT ", 0x104000ull},
1001 {"QM_ECC_MBIT_CNT ", 0x104008ull},
1002 {"QM_DFX_MB_CNT ", 0x104018ull},
1003 {"QM_DFX_DB_CNT ", 0x104028ull},
1004 {"QM_DFX_SQE_CNT ", 0x104038ull},
1005 {"QM_DFX_CQE_CNT ", 0x104048ull},
1006 {"QM_DFX_SEND_SQE_TO_ACC_CNT ", 0x104050ull},
1007 {"QM_DFX_WB_SQE_FROM_ACC_CNT ", 0x104058ull},
1008 {"QM_DFX_ACC_FINISH_CNT ", 0x104060ull},
1009 {"QM_DFX_CQE_ERR_CNT ", 0x1040b4ull},
1010 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull},
1011 {"QM_ECC_1BIT_INF ", 0x104004ull},
1012 {"QM_ECC_MBIT_INF ", 0x10400cull},
1013 {"QM_DFX_ACC_RDY_VLD0 ", 0x1040a0ull},
1014 {"QM_DFX_ACC_RDY_VLD1 ", 0x1040a4ull},
1015 {"QM_DFX_AXI_RDY_VLD ", 0x1040a8ull},
1016 {"QM_DFX_FF_ST0 ", 0x1040c8ull},
1017 {"QM_DFX_FF_ST1 ", 0x1040ccull},
1018 {"QM_DFX_FF_ST2 ", 0x1040d0ull},
1019 {"QM_DFX_FF_ST3 ", 0x1040d4ull},
1020 {"QM_DFX_FF_ST4 ", 0x1040d8ull},
1021 {"QM_DFX_FF_ST5 ", 0x1040dcull},
1022 {"QM_DFX_FF_ST6 ", 0x1040e0ull},
1023 {"QM_IN_IDLE_ST ", 0x1040e4ull},
1024 { NULL, 0}
1028 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull},
1029 { NULL, 0}
1045 seq_printf(s, "%s= 0x%08x\n", regs->reg_name, val); in qm_regs_show()
1049 return 0; in qm_regs_show()
1107 for (i = 0; i < info_size; i++, info_curr++) { in dump_show()
1108 if (i % BYTE_PER_DW == 0) in dump_show()
1119 for (i = 0; i < info_size; i += BYTE_PER_DW) { in dump_show()
1127 return 0; in dump_show()
1151 ret = kstrtou32(s, 0, &qp_id); in qm_sqc_dump()
1153 dev_err(dev, "Please input qp num (0-%d)", qm->qp_num - 1); in qm_sqc_dump()
1197 ret = kstrtou32(s, 0, &qp_id); in qm_cqc_dump()
1199 dev_err(dev, "Please input qp num (0-%d)", qm->qp_num - 1); in qm_cqc_dump()
1249 ret = qm_mb(qm, cmd, xeqc_dma, 0, 1); in qm_eqc_aeqc_dump()
1276 ret = kstrtou32(presult, 0, q_id); in q_dump_param_parse()
1278 dev_err(dev, "Please input qp num (0-%d)", qp_num - 1); in q_dump_param_parse()
1288 ret = kstrtou32(presult, 0, e_id); in q_dump_param_parse()
1290 dev_err(dev, "Please input sqe num (0-%d)", QM_Q_DEPTH - 1); in q_dump_param_parse()
1299 return 0; in q_dump_param_parse()
1365 ret = kstrtou32(s, 0, &xeqe_id); in qm_eq_aeq_dump()
1370 dev_err(dev, "Please input eqe num (0-%d)", QM_EQ_DEPTH - 1); in qm_eq_aeq_dump()
1373 dev_err(dev, "Please input aeqe num (0-%d)", QM_Q_DEPTH - 1); in qm_eq_aeq_dump()
1416 return 0; in qm_dbg_help()
1476 return 0; in qm_cmd_write()
1480 return 0; in qm_cmd_write()
1494 cmd_buf[count] = '\0'; in qm_cmd_write()
1498 *cmd_buf_tmp = '\0'; in qm_cmd_write()
1532 return 0; in qm_create_debugfs_file()
1573 for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) { in qm_log_hw_error()
1578 dev_err(dev, "%s [error status=0x%x] found\n", in qm_log_hw_error()
1670 qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC); in qm_create_qp_nolock()
1671 if (qp_id < 0) { in qm_create_qp_nolock()
1680 memset(qp->cqe, 0, sizeof(struct qm_cqe) * QM_Q_DEPTH); in qm_create_qp_nolock()
1761 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size)); in qm_qp_ctx_cfg()
1765 sqc->w8 = 0; /* rand_qc */ in qm_qp_ctx_cfg()
1768 sqc->w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type)); in qm_qp_ctx_cfg()
1770 ret = qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0); in qm_qp_ctx_cfg()
1788 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0, 4)); in qm_qp_ctx_cfg()
1792 cqc->w8 = 0; in qm_qp_ctx_cfg()
1796 ret = qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0); in qm_qp_ctx_cfg()
1821 return 0; in qm_start_qp_nolock()
1829 * After this function, qp can receive request from user. Return 0 if
1857 int ret = 0, i = 0; in qm_drain_qp()
1865 return 0; in qm_drain_qp()
1920 return 0; in qm_stop_qp_nolock()
1939 return 0; in qm_stop_qp_nolock()
1946 * This function is reverse of hisi_qm_start_qp. Return 0 if successful.
1973 * done function should clear used sqe to 0.
1994 qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0); in hisi_qp_send()
1998 return 0; in hisi_qp_send()
2009 writel(0x1, qm->io_base + QM_CACHE_WB_START); in hisi_qm_cache_wb()
2011 val, val & BIT(0), 10, 1000)) in hisi_qm_cache_wb()
2031 u8 alg_type = 0; in hisi_qm_uacce_get_queue()
2043 return 0; in hisi_qm_uacce_get_queue()
2088 * dma_mmap_coherent() requires vm_pgoff as 0 in hisi_qm_uacce_mmap()
2092 vma->vm_pgoff = 0; in hisi_qm_uacce_mmap()
2124 return 0; in qm_set_sqctype()
2138 if (qp_ctx.qc_type != 0 && qp_ctx.qc_type != 1) in hisi_qm_uacce_ioctl()
2151 return 0; in hisi_qm_uacce_ioctl()
2178 if (ret < 0) in qm_alloc_uacce()
2215 return 0; in qm_alloc_uacce()
2231 return 0; in qm_frozen()
2238 return 0; in qm_frozen()
2251 int ret = 0; in qm_try_frozen_vfs()
2318 for (i = num - 1; i >= 0; i--) { in hisi_qp_memory_uninit()
2346 return 0; in hisi_qp_memory_init()
2352 size_t qp_dma_size, off = 0; in hisi_qm_memory_init()
2353 int i, ret = 0; in hisi_qm_memory_init()
2359 } while (0) in hisi_qm_memory_init()
2387 for (i = 0; i < qm->qp_num; i++) { in hisi_qm_memory_init()
2417 qm->qp_in_used = 0; in hisi_qm_pre_init()
2449 memset(&qm->qdma, 0, sizeof(qm->qdma)); in hisi_qm_uninit()
2492 * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
2494 * (VF function number 0x2)
2512 status->eq_head = 0; in qm_init_eq_aeq_status()
2513 status->aeq_head = 0; in qm_init_eq_aeq_status()
2544 ret = qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0); in qm_eq_ctx_cfg()
2564 ret = qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0); in qm_eq_ctx_cfg()
2582 ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num); in __hisi_qm_start()
2591 ret = qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0); in __hisi_qm_start()
2595 ret = qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0); in __hisi_qm_start()
2599 writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK); in __hisi_qm_start()
2600 writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK); in __hisi_qm_start()
2602 return 0; in __hisi_qm_start()
2614 int ret = 0; in hisi_qm_start()
2626 dev_err(dev, "qp_num should not be 0\n"); in hisi_qm_start()
2648 if (ret < 0) in qm_restart()
2652 for (i = 0; i < qm->qp_num; i++) { in qm_restart()
2656 ret = qm_start_qp_nolock(qp, 0); in qm_restart()
2657 if (ret < 0) { in qm_restart()
2668 return 0; in qm_restart()
2678 for (i = 0; i < qm->qp_num; i++) { in qm_stop_started_qp()
2683 if (ret < 0) { in qm_stop_started_qp()
2690 return 0; in qm_stop_started_qp()
2702 for (i = 0; i < qm->qp_num; i++) { in qm_clear_queues()
2705 memset(qp->qdma.va, 0, qp->qdma.size); in qm_clear_queues()
2708 memset(qm->qdma.va, 0, qm->qdma.size); in qm_clear_queues()
2723 int ret = 0; in hisi_qm_stop()
2736 if (ret < 0) { in hisi_qm_stop()
2743 writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK); in hisi_qm_stop()
2744 writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK); in hisi_qm_stop()
2747 ret = hisi_qm_set_vft(qm, 0, 0, 0); in hisi_qm_stop()
2748 if (ret < 0) { in hisi_qm_stop()
2788 atomic64_set((atomic64_t *)data, 0); in qm_debugfs_atomic64_set()
2790 return 0; in qm_debugfs_atomic64_set()
2797 return 0; in qm_debugfs_atomic64_get()
2833 for (i = 0; i < ARRAY_SIZE(qm_dfx_files); i++) { in hisi_qm_debug_init()
2842 return 0; in hisi_qm_debug_init()
2860 writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); in hisi_qm_debug_regs_clear()
2861 writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); in hisi_qm_debug_regs_clear()
2867 writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE); in hisi_qm_debug_regs_clear()
2870 for (i = 0; i < CNT_CYC_REGS_NUM; i++) { in hisi_qm_debug_regs_clear()
2875 writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE); in hisi_qm_debug_regs_clear()
2962 if (!qps || qp_num <= 0) in hisi_qm_free_qps()
2965 for (i = qp_num - 1; i >= 0; i--) in hisi_qm_free_qps()
2987 int dev_node = 0; in hisi_qm_sort_devices()
2994 if (dev_node < 0) in hisi_qm_sort_devices()
2995 dev_node = 0; in hisi_qm_sort_devices()
3014 return 0; in hisi_qm_sort_devices()
3037 if (!qps || !qm_list || qp_num <= 0) in hisi_qm_alloc_qps_node()
3047 for (i = 0; i < qp_num; i++) { in hisi_qm_alloc_qps_node()
3056 ret = 0; in hisi_qm_alloc_qps_node()
3093 for (j = i; j > 0; j--) in qm_vf_q_assign()
3094 hisi_qm_set_vft(qm, j, 0, 0); in qm_vf_q_assign()
3100 return 0; in qm_vf_q_assign()
3109 ret = hisi_qm_set_vft(qm, i, 0, 0); in qm_clear_vft_config()
3113 qm->vfs_num = 0; in qm_clear_vft_config()
3115 return 0; in qm_clear_vft_config()
3137 return 0; in hisi_qm_sriov_enable()
3194 * Enable SR-IOV according to num_vfs, 0 means disable.
3198 if (num_vfs == 0) in hisi_qm_sriov_configure()
3199 return hisi_qm_sriov_disable(pdev, 0); in hisi_qm_sriov_configure()
3319 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_pf_mse()
3322 return 0; in qm_set_pf_mse()
3345 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_vf_mse()
3349 return 0; in qm_set_vf_mse()
3363 0); in qm_set_msi()
3369 return 0; in qm_set_msi()
3376 return 0; in qm_set_msi()
3386 int ret = 0; in qm_vf_reset_prepare()
3413 int delay = 0; in qm_reset_prepare_ready()
3422 return 0; in qm_reset_prepare_ready()
3450 return 0; in qm_controller_reset_prepare()
3455 u32 nfe_enb = 0; in qm_dev_ecc_mbit_handle()
3523 unsigned long long value = 0; in qm_soft_reset()
3543 return 0; in qm_soft_reset()
3552 int ret = 0; in qm_vf_reset_done()
3689 return 0; in qm_controller_reset_done()
3715 return 0; in qm_controller_reset()
3752 return 0; in qm_check_dev_error()
3766 u32 delay = 0; in hisi_qm_reset_prepare()
3905 return 0; in qm_irq_register()
3953 int flag = 0; in hisi_qm_alg_register()
3954 int ret = 0; in hisi_qm_alg_register()
4011 if (ret < 0) in hisi_qm_init()
4015 if (ret < 0) { in hisi_qm_init()
4021 if (ret < 0) { in hisi_qm_init()
4035 if (ret < 0) in hisi_qm_init()
4045 if (ret < 0) { in hisi_qm_init()
4071 return 0; in hisi_qm_init()