1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk.h>
21 	struct clk *cpu_clk;
22 	struct clk *pllp_clk;
23 	struct clk *pllx_clk;
24 	struct clk *dfll_clk;
30 	struct clk *orig_parent;  in tegra124_cpu_switch_to_dfll()
33 	ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk));  in tegra124_cpu_switch_to_dfll()
37 	orig_parent = clk_get_parent(priv->cpu_clk);  in tegra124_cpu_switch_to_dfll()
38 	clk_set_parent(priv->cpu_clk, priv->pllp_clk);  in tegra124_cpu_switch_to_dfll()
40 	ret = clk_prepare_enable(priv->dfll_clk);  in tegra124_cpu_switch_to_dfll()
44 	clk_set_parent(priv->cpu_clk, priv->dfll_clk);  in tegra124_cpu_switch_to_dfll()
49 	clk_set_parent(priv->cpu_clk, orig_parent);  in tegra124_cpu_switch_to_dfll()
62 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in tegra124_cpufreq_probe()
64 		return -ENOMEM;  in tegra124_cpufreq_probe()
68 		return -ENODEV;  in tegra124_cpufreq_probe()
72 		return -ENODEV;  in tegra124_cpufreq_probe()
74 	priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");  in tegra124_cpufreq_probe()
75 	if (IS_ERR(priv->cpu_clk)) {  in tegra124_cpufreq_probe()
76 		ret = PTR_ERR(priv->cpu_clk);  in tegra124_cpufreq_probe()
80 	priv->dfll_clk = of_clk_get_by_name(np, "dfll");  in tegra124_cpufreq_probe()
81 	if (IS_ERR(priv->dfll_clk)) {  in tegra124_cpufreq_probe()
82 		ret = PTR_ERR(priv->dfll_clk);  in tegra124_cpufreq_probe()
86 	priv->pllx_clk = of_clk_get_by_name(np, "pll_x");  in tegra124_cpufreq_probe()
87 	if (IS_ERR(priv->pllx_clk)) {  in tegra124_cpufreq_probe()
88 		ret = PTR_ERR(priv->pllx_clk);  in tegra124_cpufreq_probe()
92 	priv->pllp_clk = of_clk_get_by_name(np, "pll_p");  in tegra124_cpufreq_probe()
93 	if (IS_ERR(priv->pllp_clk)) {  in tegra124_cpufreq_probe()
94 		ret = PTR_ERR(priv->pllp_clk);  in tegra124_cpufreq_probe()
102 	cpufreq_dt_devinfo.name = "cpufreq-dt";  in tegra124_cpufreq_probe()
103 	cpufreq_dt_devinfo.parent = &pdev->dev;  in tegra124_cpufreq_probe()
105 	priv->cpufreq_dt_pdev =  in tegra124_cpufreq_probe()
107 	if (IS_ERR(priv->cpufreq_dt_pdev)) {  in tegra124_cpufreq_probe()
108 		ret = PTR_ERR(priv->cpufreq_dt_pdev);  in tegra124_cpufreq_probe()
119 	clk_put(priv->pllp_clk);  in tegra124_cpufreq_probe()
121 	clk_put(priv->pllx_clk);  in tegra124_cpufreq_probe()
123 	clk_put(priv->dfll_clk);  in tegra124_cpufreq_probe()
125 	clk_put(priv->cpu_clk);  in tegra124_cpufreq_probe()
139 	 * use during suspend and resume. So, switch the CPU clock source  in tegra124_cpufreq_suspend()
142 	err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);  in tegra124_cpufreq_suspend()
148 	clk_disable_unprepare(priv->dfll_clk);  in tegra124_cpufreq_suspend()
159 	 * Warmboot code powers up the CPU with PLLP clock source.  in tegra124_cpufreq_resume()
160 	 * Enable DFLL clock and switch CPU clock source back to DFLL.  in tegra124_cpufreq_resume()
162 	err = clk_prepare_enable(priv->dfll_clk);  in tegra124_cpufreq_resume()
168 	err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);  in tegra124_cpufreq_resume()
177 	clk_disable_unprepare(priv->dfll_clk);  in tegra124_cpufreq_resume()
190 	.driver.name	= "cpufreq-tegra124",
202 		return -ENODEV;  in tegra_cpufreq_init()
212 	pdev = platform_device_register_simple("cpufreq-tegra124", -1, NULL, 0);  in tegra_cpufreq_init()