1 // SPDX-License-Identifier: GPL-2.0+
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 #include <linux/clk.h>
26 #include "cpufreq-dt.h"
66  * each level can be associated with a CPU clock source, a CPU
123 						 struct clk *clk, u8 *divider)  in armada37xx_cpufreq_dvfs_setup()  argument
126 	struct clk *parent;  in armada37xx_cpufreq_dvfs_setup()
140 		/* Set cpu clock source, for all the level we use TBG */  in armada37xx_cpufreq_dvfs_setup()
146 		 * Set cpu divider based on the pre-computed array in  in armada37xx_cpufreq_dvfs_setup()
165 	 * Set cpu clock source, for all the level we keep the same  in armada37xx_cpufreq_dvfs_setup()
166 	 * clock source that the one already configured. For this one  in armada37xx_cpufreq_dvfs_setup()
169 	parent = clk_get_parent(clk);  in armada37xx_cpufreq_dvfs_setup()
170 	clk_set_parent(clk, parent);  in armada37xx_cpufreq_dvfs_setup()
175  * the round-up closest to the target voltage value.
181 	/* Find out the round-up closest supported voltage value */  in armada_37xx_avs_val_match()
191 		avs = ARRAY_SIZE(avs_map) - 1;  in armada_37xx_avs_val_match()
199  * - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage
201  * - L1 voltage should be about 100mv smaller than L0 voltage
202  * - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
224 	dvfs->avs[0] = l0_vdd_min;  in armada37xx_cpufreq_avs_configure()
234 			dvfs->avs[load_level] = avs_min;  in armada37xx_cpufreq_avs_configure()
240 	 * L1 voltage is equal to L0 voltage - 100mv and it must be  in armada37xx_cpufreq_avs_configure()
244 	target_vm = avs_map[l0_vdd_min] - 100;  in armada37xx_cpufreq_avs_configure()
246 	dvfs->avs[1] = armada_37xx_avs_val_match(target_vm);  in armada37xx_cpufreq_avs_configure()
249 	 * L2 & L3 voltage is equal to L0 voltage - 150mv and it must  in armada37xx_cpufreq_avs_configure()
252 	target_vm = avs_map[l0_vdd_min] - 150;  in armada37xx_cpufreq_avs_configure()
254 	dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm);  in armada37xx_cpufreq_avs_configure()
278 		avs_val = dvfs->avs[load_level];  in armada37xx_cpufreq_avs_setup()
279 		regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1),  in armada37xx_cpufreq_avs_setup()
323 	regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1);  in armada37xx_cpufreq_suspend()
324 	regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3);  in armada37xx_cpufreq_suspend()
325 	regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD,  in armada37xx_cpufreq_suspend()
326 		    &state->nb_cpu_load);  in armada37xx_cpufreq_suspend()
327 	regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod);  in armada37xx_cpufreq_suspend()
337 	armada37xx_cpufreq_disable_dvfs(state->regmap);  in armada37xx_cpufreq_resume()
339 	regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1);  in armada37xx_cpufreq_resume()
340 	regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3);  in armada37xx_cpufreq_resume()
341 	regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD,  in armada37xx_cpufreq_resume()
342 		     state->nb_cpu_load);  in armada37xx_cpufreq_resume()
349 	regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod);  in armada37xx_cpufreq_resume()
364 	struct clk *clk, *parent;  in armada37xx_cpufreq_driver_init()  local
367 		syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");  in armada37xx_cpufreq_driver_init()
370 		return -ENODEV;  in armada37xx_cpufreq_driver_init()
373 		syscon_regmap_lookup_by_compatible("marvell,armada-3700-avs");  in armada37xx_cpufreq_driver_init()
391 		return -ENODEV;  in armada37xx_cpufreq_driver_init()
394 	clk = clk_get(cpu_dev, 0);  in armada37xx_cpufreq_driver_init()
395 	if (IS_ERR(clk)) {  in armada37xx_cpufreq_driver_init()
397 		return PTR_ERR(clk);  in armada37xx_cpufreq_driver_init()
400 	parent = clk_get_parent(clk);  in armada37xx_cpufreq_driver_init()
403 		clk_put(clk);  in armada37xx_cpufreq_driver_init()
412 		clk_put(clk);  in armada37xx_cpufreq_driver_init()
413 		return -EINVAL;  in armada37xx_cpufreq_driver_init()
417 	cur_frequency = clk_get_rate(clk);  in armada37xx_cpufreq_driver_init()
420 		clk_put(clk);  in armada37xx_cpufreq_driver_init()
421 		return -EINVAL;  in armada37xx_cpufreq_driver_init()
426 		clk_put(clk);  in armada37xx_cpufreq_driver_init()
427 		return -EINVAL;  in armada37xx_cpufreq_driver_init()
433 		clk_put(clk);  in armada37xx_cpufreq_driver_init()
434 		return -ENOMEM;  in armada37xx_cpufreq_driver_init()
437 	armada37xx_cpufreq_state->regmap = nb_pm_base;  in armada37xx_cpufreq_driver_init()
442 	armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);  in armada37xx_cpufreq_driver_init()
443 	clk_put(clk);  in armada37xx_cpufreq_driver_init()
447 		unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;  in armada37xx_cpufreq_driver_init()
448 		freq = base_frequency / dvfs->divider[load_lvl];  in armada37xx_cpufreq_driver_init()
463 	pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata,  in armada37xx_cpufreq_driver_init()
474 	/* clean-up the already added opp before leaving */  in armada37xx_cpufreq_driver_init()
475 	while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {  in armada37xx_cpufreq_driver_init()
476 		freq = cur_frequency / dvfs->divider[load_lvl];  in armada37xx_cpufreq_driver_init()
488 	{ .compatible = "marvell,armada-3700-nb-pm" },
493 MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");