1 // SPDX-License-Identifier: GPL-2.0
3  * STM32 Timer Encoder and Counter driver
10 #include <linux/counter.h>
11 #include <linux/mfd/stm32-timers.h>
31 	struct counter_device counter;  member
40  * enum stm32_count_function - enumerates stm32 timer counter encoder modes
47 	STM32_COUNT_SLAVE_MODE_DISABLED = -1,
59 static int stm32_count_read(struct counter_device *counter,  in stm32_count_read()  argument
62 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_read()
65 	regmap_read(priv->regmap, TIM_CNT, &cnt);  in stm32_count_read()
71 static int stm32_count_write(struct counter_device *counter,  in stm32_count_write()  argument
75 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_write()
77 	if (val > priv->ceiling)  in stm32_count_write()
78 		return -EINVAL;  in stm32_count_write()
80 	return regmap_write(priv->regmap, TIM_CNT, val);  in stm32_count_write()
83 static int stm32_count_function_get(struct counter_device *counter,  in stm32_count_function_get()  argument
87 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_function_get()
90 	regmap_read(priv->regmap, TIM_SMCR, &smcr);  in stm32_count_function_get()
104 	return -EINVAL;  in stm32_count_function_get()
107 static int stm32_count_function_set(struct counter_device *counter,  in stm32_count_function_set()  argument
111 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_function_set()
130 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_function_set()
132 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_count_function_set()
135 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);  in stm32_count_function_set()
136 	regmap_write(priv->regmap, TIM_ARR, priv->ceiling);  in stm32_count_function_set()
138 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);  in stm32_count_function_set()
141 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);  in stm32_count_function_set()
144 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);  in stm32_count_function_set()
149 static ssize_t stm32_count_direction_read(struct counter_device *counter,  in stm32_count_direction_read()  argument
153 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_direction_read()
157 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_direction_read()
163 static ssize_t stm32_count_ceiling_read(struct counter_device *counter,  in stm32_count_ceiling_read()  argument
167 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_ceiling_read()
170 	regmap_read(priv->regmap, TIM_ARR, &arr);  in stm32_count_ceiling_read()
175 static ssize_t stm32_count_ceiling_write(struct counter_device *counter,  in stm32_count_ceiling_write()  argument
180 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_ceiling_write()
189 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);  in stm32_count_ceiling_write()
190 	regmap_write(priv->regmap, TIM_ARR, ceiling);  in stm32_count_ceiling_write()
192 	priv->ceiling = ceiling;  in stm32_count_ceiling_write()
196 static ssize_t stm32_count_enable_read(struct counter_device *counter,  in stm32_count_enable_read()  argument
200 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_enable_read()
203 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_read()
208 static ssize_t stm32_count_enable_write(struct counter_device *counter,  in stm32_count_enable_write()  argument
213 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_enable_write()
223 		regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_write()
225 			clk_enable(priv->clk);  in stm32_count_enable_write()
227 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,  in stm32_count_enable_write()
230 		regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_write()
231 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_count_enable_write()
233 			clk_disable(priv->clk);  in stm32_count_enable_write()
237 	priv->enabled = enable;  in stm32_count_enable_write()
269 static int stm32_action_get(struct counter_device *counter,  in stm32_action_get()  argument
280 	err = stm32_count_function_get(counter, count, &function);  in stm32_action_get()
287 		if (synapse->signal->id == count->synapses[0].signal->id)  in stm32_action_get()
292 		if (synapse->signal->id == count->synapses[1].signal->id)  in stm32_action_get()
349 	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);  in stm32_timer_cnt_probe()
350 	struct device *dev = &pdev->dev;  in stm32_timer_cnt_probe()
354 		return -EINVAL;  in stm32_timer_cnt_probe()
358 		return -ENOMEM;  in stm32_timer_cnt_probe()
360 	priv->regmap = ddata->regmap;  in stm32_timer_cnt_probe()
361 	priv->clk = ddata->clk;  in stm32_timer_cnt_probe()
362 	priv->ceiling = ddata->max_arr;  in stm32_timer_cnt_probe()
364 	priv->counter.name = dev_name(dev);  in stm32_timer_cnt_probe()
365 	priv->counter.parent = dev;  in stm32_timer_cnt_probe()
366 	priv->counter.ops = &stm32_timer_cnt_ops;  in stm32_timer_cnt_probe()
367 	priv->counter.counts = &stm32_counts;  in stm32_timer_cnt_probe()
368 	priv->counter.num_counts = 1;  in stm32_timer_cnt_probe()
369 	priv->counter.signals = stm32_signals;  in stm32_timer_cnt_probe()
370 	priv->counter.num_signals = ARRAY_SIZE(stm32_signals);  in stm32_timer_cnt_probe()
371 	priv->counter.priv = priv;  in stm32_timer_cnt_probe()
375 	/* Register Counter device */  in stm32_timer_cnt_probe()
376 	return devm_counter_register(dev, &priv->counter);  in stm32_timer_cnt_probe()
383 	/* Only take care of enabled counter: don't disturb other MFD child */  in stm32_timer_cnt_suspend()
384 	if (priv->enabled) {  in stm32_timer_cnt_suspend()
386 		regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);  in stm32_timer_cnt_suspend()
387 		regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);  in stm32_timer_cnt_suspend()
388 		regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);  in stm32_timer_cnt_suspend()
389 		regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);  in stm32_timer_cnt_suspend()
391 		/* Disable the counter */  in stm32_timer_cnt_suspend()
392 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_timer_cnt_suspend()
393 		clk_disable(priv->clk);  in stm32_timer_cnt_suspend()
408 	if (priv->enabled) {  in stm32_timer_cnt_resume()
409 		clk_enable(priv->clk);  in stm32_timer_cnt_resume()
412 		regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);  in stm32_timer_cnt_resume()
413 		regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);  in stm32_timer_cnt_resume()
414 		regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);  in stm32_timer_cnt_resume()
416 		/* Also re-enables the counter */  in stm32_timer_cnt_resume()
417 		regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);  in stm32_timer_cnt_resume()
427 	{ .compatible = "st,stm32-timer-counter", },
435 		.name = "stm32-timer-counter",
443 MODULE_ALIAS("platform:stm32-timer-counter");
444 MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");