4  * Timer COH 901 328, runs the OS timer interrupt.
27  * APP side special timer registers
28  * This timer contains four timers which can fire an interrupt each.
29  * OS (operating system) timer @ 32768 Hz
30  * DD (device driver) timer @ 1 kHz
31  * GP1 (general purpose 1) timer @ 1MHz
32  * GP2 (general purpose 2) timer @ 1MHz
35 /* Reset OS Timer 32bit (-/W) */
38 /* Enable OS Timer 32bit (-/W) */
41 /* Disable OS Timer 32bit (-/W) */
44 /* OS Timer Mode Register 32bit (-/W) */
48 /* OS Timer Status Register 32bit (R/-) */
59 /* OS Timer Current Count Register 32bit (R/-) */
61 /* OS Timer Terminal Count Register 32bit (R/W) */
63 /* OS Timer Interrupt Enable Register 32bit (-/W) */
67 /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
71 /* Reset DD Timer 32bit (-/W) */
74 /* Enable DD Timer 32bit (-/W) */
77 /* Disable DD Timer 32bit (-/W) */
80 /* DD Timer Mode Register 32bit (-/W) */
84 /* DD Timer Status Register 32bit (R/-) */
95 /* DD Timer Current Count Register 32bit (R/-) */
97 /* DD Timer Terminal Count Register 32bit (R/W) */
99 /* DD Timer Interrupt Enable Register 32bit (-/W) */
103 /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
107 /* Reset GP1 Timer 32bit (-/W) */
110 /* Enable GP1 Timer 32bit (-/W) */
113 /* Disable GP1 Timer 32bit (-/W) */
116 /* GP1 Timer Mode Register 32bit (-/W) */
120 /* GP1 Timer Status Register 32bit (R/-) */
131 /* GP1 Timer Current Count Register 32bit (R/-) */
133 /* GP1 Timer Terminal Count Register 32bit (R/W) */
135 /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
139 /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
143 /* Reset GP2 Timer 32bit (-/W) */
146 /* Enable GP2 Timer 32bit (-/W) */
149 /* Disable GP2 Timer 32bit (-/W) */
152 /* GP2 Timer Mode Register 32bit (-/W) */
156 /* GP2 Timer Status Register 32bit (R/-) */
167 /* GP2 Timer Current Count Register 32bit (R/-) */
169 /* GP2 Timer Terminal Count Register 32bit (R/W) */
171 /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
175 /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
202  * If we have oneshot timer active, the oneshot scheduling function
227 	/* Enable interrupts for this timer */  in u300_set_oneshot()
230 	/* Enable timer */  in u300_set_oneshot()
254 	 * Set continuous mode, so the timer keeps triggering  in u300_set_periodic()
259 	/* Enable timer interrupts */  in u300_set_periodic()
262 	/* Then enable the OS timer again */  in u300_set_periodic()
269  * The app timer in one shot mode obviously has to be reprogrammed
271  * the interrupt disable + timer disable commands with a reset command,
273  * the timer is very sensitive to the instruction order, though you don't
286 	/* Reset the General Purpose timer 1. */  in u300_set_next_event()
293 	 * the timer will tilt if you don't!)  in u300_set_next_event()
297 	/* Enable timer interrupts */  in u300_set_next_event()
300 	/* Then enable the OS timer again */  in u300_set_next_event()
307 	/* Use general purpose timer 1 as clock event */
321 /* Clock event timer interrupt handler */
325 	/* ACK/Clear timer IRQ for the APP GPT1 Timer */  in u300_timer_interrupt()
365 		pr_err("could not ioremap system timer\n");  in u300_timer_init_of()
369 	/* Get the IRQ for the GP1 timer */  in u300_timer_init_of()
372 		pr_err("no IRQ for system timer\n");  in u300_timer_init_of()
376 	pr_info("U300 GP1 timer @ base: %p, IRQ: %u\n", u300_timer_base, irq);  in u300_timer_init_of()
412 	/* Reset the General Purpose timer 1. */  in u300_timer_init_of()
418 			  IRQF_TIMER | IRQF_IRQPOLL, "U300 Timer Tick", NULL);  in u300_timer_init_of()
422 	/* Reset the General Purpose timer 2 */  in u300_timer_init_of()
425 	/* Set this timer to run around forever */  in u300_timer_init_of()
430 	/* Disable timer interrupts */  in u300_timer_init_of()
433 	/* Then enable the GP2 timer to use as a free running us counter */  in u300_timer_init_of()
437 	/* Use general purpose timer 2 as clock source */  in u300_timer_init_of()
441 		pr_err("timer: failed to initialize U300 clock source\n");  in u300_timer_init_of()