clk/zynqmp/clk-mux-zynqmp.c

1 // SPDX-License-Identifier: GPL-2.0
5  *  Copyright (C) 2016-2018 Xilinx
8 #include <linux/clk-provider.h>
10 #include "clk-zynqmp.h"
13  * DOC: basic adjustable multiplexer clock that cannot gate
15  * Traits of this clock:
16  * prepare - clk_prepare only ensures that parents are prepared
17  * enable - clk_enable only ensures that parents are enabled
18  * rate - rate is only affected by parent switching.  No clk_set_rate support
19  * parent - parent is adjustable through clk_set_parent
23  * struct zynqmp_clk_mux - multiplexer clock
25  * @hw:		handle between common and hardware-specific interfaces
26  * @flags:	hardware-specific flags
27  * @clk_id:	Id of clock
38  * zynqmp_clk_mux_get_parent() - Get parent of clock
39  * @hw:		handle between common and hardware-specific interfaces
47 	u32 clk_id = mux->clk_id;  in zynqmp_clk_mux_get_parent()
54 		pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n",  in zynqmp_clk_mux_get_parent()
61  * zynqmp_clk_mux_set_parent() - Set parent of clock
62  * @hw:		handle between common and hardware-specific interfaces
71 	u32 clk_id = mux->clk_id;  in zynqmp_clk_mux_set_parent()
77 		pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n",  in zynqmp_clk_mux_set_parent()
94  * zynqmp_clk_register_mux() - Register a mux table with the clock
96  * @name:		Name of this clock
97  * @clk_id:		Id of this clock
98  * @parents:		Name of this clock's parents
100  * @nodes:		Clock topology node
102  * Return: clock hardware of the registered clock mux
104 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,  in zynqmp_clk_register_mux()  argument
116 		return ERR_PTR(-ENOMEM);  in zynqmp_clk_register_mux()
118 	init.name = name;  in zynqmp_clk_register_mux()
119 	if (nodes->type_flag & CLK_MUX_READ_ONLY)  in zynqmp_clk_register_mux()
123 	init.flags = nodes->flag;  in zynqmp_clk_register_mux()
126 	mux->flags = nodes->type_flag;  in zynqmp_clk_register_mux()
127 	mux->hw.init = &init;  in zynqmp_clk_register_mux()
128 	mux->clk_id = clk_id;  in zynqmp_clk_register_mux()
130 	hw = &mux->hw;  in zynqmp_clk_register_mux()