clk/ti/dpll.c

2  * OMAP DPLL clock support
153  * _register_dpll - low level registration of a DPLL clock
157  * Finalizes DPLL registration process. In case a failure (clk-ref or
221  * Initializes a DPLL x 2 clock from device tree data.
278  * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
279  * @node: device node containing the DPLL info
280  * @ops: ops for the DPLL
281  * @ddt: DPLL data template to use
283  * Initializes a DPLL clock from device tree data.
326 	 * Special case for OMAP2 DPLL, register order is different due to  in of_ti_dpll_setup()
378 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
387 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
414 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
433 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
453 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
475 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
495 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
516 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
535 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
558 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
579 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
599 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
619 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
640 	       "ti,am3-dpll-no-gate-j-type-clock",
659 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
677 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
692 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",