clk/tegra/clk-tegra30.c

1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/tegra30-car.h>
19 #include "clk-id.h"
583 	{ .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
593 	{ .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
594 	{ .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
595 	{ .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
599 	{ .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
600 	{ .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
602 	{ .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
603 	{ .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
604 	{ .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
605 	{ .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
606 	{ .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
608 	{ .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
609 	{ .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
610 	{ .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
611 	{ .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
612 	{ .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
615 	{ .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
616 	{ .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
617 	{ .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
618 	{ .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
619 	{ .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
620 	{ .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
621 	{ .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
622 	{ .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
623 	{ .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
624 	{ .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
625 	{ .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
626 	{ .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
627 	{ .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
643 	{ .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
655 	{ .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
656 	{ .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
657 	{ .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
658 	{ .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
659 	{ .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
665 	{ .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
666 	{ .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
667 	{ .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
668 	{ .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
669 	{ .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
1040 	/* emc */  in tegra30_periph_clk_init()
1045 	clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,  in tegra30_periph_clk_init()
1062 		clks[data->clk_id] = clk;  in tegra30_periph_clk_init()
1067 		clk = tegra_clk_register_periph_nodiv(data->name,  in tegra30_periph_clk_init()
1068 					data->p.parent_names,  in tegra30_periph_clk_init()
1069 					data->num_parents, &data->periph,  in tegra30_periph_clk_init()
1070 					clk_base, data->offset);  in tegra30_periph_clk_init()
1071 		clks[data->clk_id] = clk;  in tegra30_periph_clk_init()
1077 /* Tegra30 CPU clock and reset control functions */
1274 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1275 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1276 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1277 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1279 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1280 	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1290 	{ .compatible = "nvidia,tegra30-pmc" },
1310 	if (clkspec->args[0] == TEGRA30_CLK_EMC) {  in tegra30_clk_src_onecell_get()
1312 			return ERR_PTR(-EPROBE_DEFER);  in tegra30_clk_src_onecell_get()
1324 		pr_err("ioremap tegra30 CAR failed\n");  in tegra30_clock_init()
1367 CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);