Lines Matching +full:timing +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
47 * When we change the timing to a timing with a parent that has the same
49 * timing that has a different clock source.
101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
116 struct emc_timing *timing = NULL; in emc_determine_rate() local
121 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
122 if (tegra->timings[k].ram_code == ram_code) in emc_determine_rate()
126 for (t = k; t < tegra->num_timings; t++) { in emc_determine_rate()
127 if (tegra->timings[t].ram_code != ram_code) in emc_determine_rate()
132 timing = tegra->timings + i; in emc_determine_rate()
134 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
137 if (timing->rate > req->max_rate) { in emc_determine_rate()
139 req->rate = tegra->timings[i - 1].rate; in emc_determine_rate()
143 if (timing->rate < req->min_rate) in emc_determine_rate()
146 req->rate = timing->rate; in emc_determine_rate()
150 if (timing) { in emc_determine_rate()
151 req->rate = timing->rate; in emc_determine_rate()
155 req->rate = clk_hw_get_rate(hw); in emc_determine_rate()
166 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_get_parent()
176 if (tegra->emc) in emc_ensure_emc_driver()
177 return tegra->emc; in emc_ensure_emc_driver()
179 if (!tegra->emc_node) in emc_ensure_emc_driver()
182 pdev = of_find_device_by_node(tegra->emc_node); in emc_ensure_emc_driver()
189 of_node_put(tegra->emc_node); in emc_ensure_emc_driver()
190 tegra->emc_node = NULL; in emc_ensure_emc_driver()
192 tegra->emc = platform_get_drvdata(pdev); in emc_ensure_emc_driver()
193 if (!tegra->emc) { in emc_ensure_emc_driver()
198 return tegra->emc; in emc_ensure_emc_driver()
202 struct emc_timing *timing) in emc_set_timing() argument
211 return -ENOENT; in emc_set_timing()
213 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate, in emc_set_timing()
214 timing->parent_rate, __clk_get_name(timing->parent)); in emc_set_timing()
216 if (emc_get_parent(&tegra->hw) == timing->parent_index && in emc_set_timing()
217 clk_get_rate(timing->parent) != timing->parent_rate) { in emc_set_timing()
219 __clk_get_name(timing->parent), in emc_set_timing()
220 clk_get_rate(timing->parent), in emc_set_timing()
221 timing->parent_rate); in emc_set_timing()
222 return -EINVAL; in emc_set_timing()
225 tegra->changing_timing = true; in emc_set_timing()
227 err = clk_set_rate(timing->parent, timing->parent_rate); in emc_set_timing()
230 __clk_get_name(timing->parent), timing->parent_rate, in emc_set_timing()
236 err = clk_prepare_enable(timing->parent); in emc_set_timing()
242 div = timing->parent_rate / (timing->rate / 2) - 2; in emc_set_timing()
244 err = tegra_emc_prepare_timing_change(emc, timing->rate); in emc_set_timing()
248 spin_lock_irqsave(tegra->lock, flags); in emc_set_timing()
250 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
253 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index); in emc_set_timing()
258 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC); in emc_set_timing()
260 spin_unlock_irqrestore(tegra->lock, flags); in emc_set_timing()
262 tegra_emc_complete_timing_change(emc, timing->rate); in emc_set_timing()
264 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); in emc_set_timing()
265 clk_disable_unprepare(tegra->prev_parent); in emc_set_timing()
267 tegra->prev_parent = timing->parent; in emc_set_timing()
268 tegra->changing_timing = false; in emc_set_timing()
274 * Get backup timing to use as an intermediate step when a change between
276 * find a timing with a higher clock rate to avoid a rate below any set rate
284 struct emc_timing *timing; in get_backup_timing() local
286 for (i = timing_index+1; i < tegra->num_timings; i++) { in get_backup_timing()
287 timing = tegra->timings + i; in get_backup_timing()
288 if (timing->ram_code != ram_code) in get_backup_timing()
291 if (emc_parent_clk_sources[timing->parent_index] != in get_backup_timing()
293 tegra->timings[timing_index].parent_index]) in get_backup_timing()
294 return timing; in get_backup_timing()
297 for (i = timing_index-1; i >= 0; --i) { in get_backup_timing()
298 timing = tegra->timings + i; in get_backup_timing()
299 if (timing->ram_code != ram_code) in get_backup_timing()
302 if (emc_parent_clk_sources[timing->parent_index] != in get_backup_timing()
304 tegra->timings[timing_index].parent_index]) in get_backup_timing()
305 return timing; in get_backup_timing()
315 struct emc_timing *timing = NULL; in emc_set_rate() local
329 if (tegra->changing_timing) in emc_set_rate()
332 for (i = 0; i < tegra->num_timings; i++) { in emc_set_rate()
333 if (tegra->timings[i].rate == rate && in emc_set_rate()
334 tegra->timings[i].ram_code == ram_code) { in emc_set_rate()
335 timing = tegra->timings + i; in emc_set_rate()
340 if (!timing) { in emc_set_rate()
342 return -EINVAL; in emc_set_rate()
346 emc_parent_clk_sources[timing->parent_index] && in emc_set_rate()
347 clk_get_rate(timing->parent) != timing->parent_rate) { in emc_set_rate()
357 pr_err("cannot find backup timing\n"); in emc_set_rate()
358 return -EINVAL; in emc_set_rate()
362 backup_timing->rate, rate); in emc_set_rate()
366 pr_err("cannot set backup timing: %d\n", err); in emc_set_rate()
371 return emc_set_timing(tegra, timing); in emc_set_rate()
377 struct emc_timing *timing, in load_one_timing_from_dt() argument
383 err = of_property_read_u32(node, "clock-frequency", &tmp); in load_one_timing_from_dt()
385 pr_err("timing %pOF: failed to read rate\n", node); in load_one_timing_from_dt()
389 timing->rate = tmp; in load_one_timing_from_dt()
391 err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp); in load_one_timing_from_dt()
393 pr_err("timing %pOF: failed to read parent rate\n", node); in load_one_timing_from_dt()
397 timing->parent_rate = tmp; in load_one_timing_from_dt()
399 timing->parent = of_clk_get_by_name(node, "emc-parent"); in load_one_timing_from_dt()
400 if (IS_ERR(timing->parent)) { in load_one_timing_from_dt()
401 pr_err("timing %pOF: failed to get parent clock\n", node); in load_one_timing_from_dt()
402 return PTR_ERR(timing->parent); in load_one_timing_from_dt()
405 timing->parent_index = 0xff; in load_one_timing_from_dt()
407 __clk_get_name(timing->parent)); in load_one_timing_from_dt()
409 pr_err("timing %pOF: %s is not a valid parent\n", in load_one_timing_from_dt()
410 node, __clk_get_name(timing->parent)); in load_one_timing_from_dt()
411 clk_put(timing->parent); in load_one_timing_from_dt()
412 return -EINVAL; in load_one_timing_from_dt()
415 timing->parent_index = i; in load_one_timing_from_dt()
424 if (a->rate < b->rate) in cmp_timings()
425 return -1; in cmp_timings()
426 else if (a->rate == b->rate) in cmp_timings()
442 size = (tegra->num_timings + child_count) * sizeof(struct emc_timing); in load_timings_from_dt()
444 tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL); in load_timings_from_dt()
445 if (!tegra->timings) in load_timings_from_dt()
446 return -ENOMEM; in load_timings_from_dt()
448 timings_ptr = tegra->timings + tegra->num_timings; in load_timings_from_dt()
449 tegra->num_timings += child_count; in load_timings_from_dt()
452 struct emc_timing *timing = timings_ptr + (i++); in load_timings_from_dt() local
454 err = load_one_timing_from_dt(tegra, timing, child); in load_timings_from_dt()
460 timing->ram_code = ram_code; in load_timings_from_dt()
488 return ERR_PTR(-ENOMEM); in tegra_clk_register_emc()
490 tegra->clk_regs = base; in tegra_clk_register_emc()
491 tegra->lock = lock; in tegra_clk_register_emc()
493 tegra->num_timings = 0; in tegra_clk_register_emc()
496 err = of_property_read_u32(node, "nvidia,ram-code", in tegra_clk_register_emc()
512 if (tegra->num_timings == 0) in tegra_clk_register_emc()
515 tegra->emc_node = of_parse_phandle(np, in tegra_clk_register_emc()
516 "nvidia,external-memory-controller", 0); in tegra_clk_register_emc()
517 if (!tegra->emc_node) in tegra_clk_register_emc()
526 tegra->hw.init = &init; in tegra_clk_register_emc()
528 clk = clk_register(NULL, &tegra->hw); in tegra_clk_register_emc()
532 tegra->prev_parent = clk_hw_get_parent_by_index( in tegra_clk_register_emc()
533 &tegra->hw, emc_get_parent(&tegra->hw))->clk; in tegra_clk_register_emc()
534 tegra->changing_timing = false; in tegra_clk_register_emc()
537 clk_register_clkdev(clk, "emc", "tegra-clk-debug"); in tegra_clk_register_emc()