Lines Matching +full:modulator +full:- +full:sel
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
244 #define mask(w) ((1 << (w)) - 1)
245 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
246 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
247 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
248 mask(p->params->div_nmp->divp_width))
249 #define sdm_din_mask(p) p->params->sdm_din_mask
250 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
252 #define divm_shift(p) (p)->params->div_nmp->divm_shift
253 #define divn_shift(p) (p)->params->div_nmp->divn_shift
254 #define divp_shift(p) (p)->params->div_nmp->divp_shift
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
287 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
298 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) in clk_pll_wait_for_lock()
304 lock_addr += pll->params->misc_reg; in clk_pll_wait_for_lock()
306 lock_addr += pll->params->base_reg; in clk_pll_wait_for_lock()
308 lock_mask = pll->params->lock_mask; in clk_pll_wait_for_lock()
310 for (i = 0; i < pll->params->lock_delay; i++) { in clk_pll_wait_for_lock()
320 clk_hw_get_name(&pll->hw)); in clk_pll_wait_for_lock()
322 return -1; in clk_pll_wait_for_lock()
332 u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in pllm_clk_is_gated_by_pmc()
345 * settings, including the enable-state. The PLLM is enabled when in clk_pll_is_enabled()
348 if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll)) in clk_pll_is_enabled()
361 if (pll->params->iddq_reg) { in _clk_pll_enable()
362 val = pll_readl(pll->params->iddq_reg, pll); in _clk_pll_enable()
363 val &= ~BIT(pll->params->iddq_bit_idx); in _clk_pll_enable()
364 pll_writel(val, pll->params->iddq_reg, pll); in _clk_pll_enable()
368 if (pll->params->reset_reg) { in _clk_pll_enable()
369 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_enable()
370 val &= ~BIT(pll->params->reset_bit_idx); in _clk_pll_enable()
371 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_enable()
377 if (pll->params->flags & TEGRA_PLL_BYPASS) in _clk_pll_enable()
382 if (pll->params->flags & TEGRA_PLLM) { in _clk_pll_enable()
383 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
385 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
395 if (pll->params->flags & TEGRA_PLL_BYPASS) in _clk_pll_disable()
400 if (pll->params->flags & TEGRA_PLLM) { in _clk_pll_disable()
401 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
403 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
406 if (pll->params->reset_reg) { in _clk_pll_disable()
407 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_disable()
408 val |= BIT(pll->params->reset_bit_idx); in _clk_pll_disable()
409 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_disable()
412 if (pll->params->iddq_reg) { in _clk_pll_disable()
413 val = pll_readl(pll->params->iddq_reg, pll); in _clk_pll_disable()
414 val |= BIT(pll->params->iddq_bit_idx); in _clk_pll_disable()
415 pll_writel(val, pll->params->iddq_reg, pll); in _clk_pll_disable()
422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { in pll_clk_start_ss()
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); in pll_clk_start_ss()
425 val |= pll->params->ssc_ctrl_en_mask; in pll_clk_start_ss()
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll); in pll_clk_start_ss()
432 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { in pll_clk_stop_ss()
433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); in pll_clk_stop_ss()
435 val &= ~pll->params->ssc_ctrl_en_mask; in pll_clk_stop_ss()
436 pll_writel(val, pll->params->ssc_ctrl_reg, pll); in pll_clk_stop_ss()
449 if (pll->lock) in clk_pll_enable()
450 spin_lock_irqsave(pll->lock, flags); in clk_pll_enable()
458 if (pll->lock) in clk_pll_enable()
459 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_enable()
469 if (pll->lock) in clk_pll_disable()
470 spin_lock_irqsave(pll->lock, flags); in clk_pll_disable()
476 if (pll->lock) in clk_pll_disable()
477 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_disable()
483 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; in _p_div_to_hw()
486 while (p_tohw->pdiv) { in _p_div_to_hw()
487 if (p_div <= p_tohw->pdiv) in _p_div_to_hw()
488 return p_tohw->hw_val; in _p_div_to_hw()
491 return -EINVAL; in _p_div_to_hw()
493 return -EINVAL; in _p_div_to_hw()
498 return _p_div_to_hw(&pll->hw, p_div); in tegra_pll_p_div_to_hw()
504 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; in _hw_to_p_div()
507 while (p_tohw->pdiv) { in _hw_to_p_div()
508 if (p_div_hw == p_tohw->hw_val) in _hw_to_p_div()
509 return p_tohw->pdiv; in _hw_to_p_div()
512 return -EINVAL; in _hw_to_p_div()
523 struct tegra_clk_pll_freq_table *sel; in _get_table_rate() local
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()
527 if (sel->input_rate == parent_rate && in _get_table_rate()
528 sel->output_rate == rate) in _get_table_rate()
531 if (sel->input_rate == 0) in _get_table_rate()
532 return -EINVAL; in _get_table_rate()
534 if (pll->params->pdiv_tohw) { in _get_table_rate()
535 p = _p_div_to_hw(hw, sel->p); in _get_table_rate()
539 p = ilog2(sel->p); in _get_table_rate()
542 cfg->input_rate = sel->input_rate; in _get_table_rate()
543 cfg->output_rate = sel->output_rate; in _get_table_rate()
544 cfg->m = sel->m; in _get_table_rate()
545 cfg->n = sel->n; in _get_table_rate()
546 cfg->p = p; in _get_table_rate()
547 cfg->cpcon = sel->cpcon; in _get_table_rate()
548 cfg->sdm_data = sel->sdm_data; in _get_table_rate()
587 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; in _calc_rate()
588 cfg->output_rate <<= 1) in _calc_rate()
591 cfg->m = parent_rate / cfreq; in _calc_rate()
592 cfg->n = cfg->output_rate / cfreq; in _calc_rate()
593 cfg->cpcon = OUT_OF_TABLE_CPCON; in _calc_rate()
595 if (cfg->m == 0 || cfg->m > divm_max(pll) || in _calc_rate()
596 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) || in _calc_rate()
597 cfg->output_rate > pll->params->vco_max) { in _calc_rate()
598 return -EINVAL; in _calc_rate()
601 cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m); in _calc_rate()
602 cfg->output_rate >>= p_div; in _calc_rate()
604 if (pll->params->pdiv_tohw) { in _calc_rate()
609 cfg->p = ret; in _calc_rate()
611 cfg->p = p_div; in _calc_rate()
617 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
618 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
619 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
631 if (!pll->params->sdm_din_reg) in clk_pll_set_sdm_data()
634 if (cfg->sdm_data) { in clk_pll_set_sdm_data()
636 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); in clk_pll_set_sdm_data()
643 if (cfg->sdm_data == 0 && enabled) in clk_pll_set_sdm_data()
644 val &= ~pll->params->sdm_ctrl_en_mask; in clk_pll_set_sdm_data()
646 if (cfg->sdm_data != 0 && !enabled) in clk_pll_set_sdm_data()
647 val |= pll->params->sdm_ctrl_en_mask; in clk_pll_set_sdm_data()
656 struct tegra_clk_pll_params *params = pll->params; in _update_pll_mnp()
657 struct div_nmp *div_nmp = params->div_nmp; in _update_pll_mnp()
659 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in _update_pll_mnp()
662 val = pll_override_readl(params->pmc_divp_reg, pll); in _update_pll_mnp()
663 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); in _update_pll_mnp()
664 val |= cfg->p << div_nmp->override_divp_shift; in _update_pll_mnp()
665 pll_override_writel(val, params->pmc_divp_reg, pll); in _update_pll_mnp()
667 val = pll_override_readl(params->pmc_divnm_reg, pll); in _update_pll_mnp()
668 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | in _update_pll_mnp()
669 (divn_mask(pll) << div_nmp->override_divn_shift)); in _update_pll_mnp()
670 val |= (cfg->m << div_nmp->override_divm_shift) | in _update_pll_mnp()
671 (cfg->n << div_nmp->override_divn_shift); in _update_pll_mnp()
672 pll_override_writel(val, params->pmc_divnm_reg, pll); in _update_pll_mnp()
679 val |= (cfg->m << divm_shift(pll)) | in _update_pll_mnp()
680 (cfg->n << divn_shift(pll)) | in _update_pll_mnp()
681 (cfg->p << divp_shift(pll)); in _update_pll_mnp()
685 clk_pll_set_sdm_data(&pll->hw, cfg); in _update_pll_mnp()
693 struct tegra_clk_pll_params *params = pll->params; in _get_pll_mnp()
694 struct div_nmp *div_nmp = params->div_nmp; in _get_pll_mnp()
698 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in _get_pll_mnp()
701 val = pll_override_readl(params->pmc_divp_reg, pll); in _get_pll_mnp()
702 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); in _get_pll_mnp()
704 val = pll_override_readl(params->pmc_divnm_reg, pll); in _get_pll_mnp()
705 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); in _get_pll_mnp()
706 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); in _get_pll_mnp()
710 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); in _get_pll_mnp()
711 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); in _get_pll_mnp()
712 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); in _get_pll_mnp()
714 if (pll->params->sdm_din_reg) { in _get_pll_mnp()
718 cfg->sdm_data = sdin_din_to_data(val); in _get_pll_mnp()
733 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; in _update_pll_cpcon()
735 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { in _update_pll_cpcon()
737 if (cfg->n >= PLLDU_LFCON_SET_DIVN) in _update_pll_cpcon()
739 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { in _update_pll_cpcon()
741 if (rate >= (pll->params->vco_max >> 1)) in _update_pll_cpcon()
757 if (state && pll->params->pre_rate_change) { in _program_pll()
758 ret = pll->params->pre_rate_change(); in _program_pll()
765 if (state && pll->params->defaults_set && pll->params->dyn_ramp && in _program_pll()
766 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { in _program_pll()
767 ret = pll->params->dyn_ramp(pll, cfg); in _program_pll()
777 if (!pll->params->defaults_set && pll->params->set_defaults) in _program_pll()
778 pll->params->set_defaults(pll); in _program_pll()
782 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) in _program_pll()
792 if (state && pll->params->post_rate_change) in _program_pll()
793 pll->params->post_rate_change(); in _program_pll()
806 if (pll->params->flags & TEGRA_PLL_FIXED) { in clk_pll_set_rate()
807 if (rate != pll->params->fixed_rate) { in clk_pll_set_rate()
810 pll->params->fixed_rate, rate); in clk_pll_set_rate()
811 return -EINVAL; in clk_pll_set_rate()
817 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { in clk_pll_set_rate()
821 return -EINVAL; in clk_pll_set_rate()
823 if (pll->lock) in clk_pll_set_rate()
824 spin_lock_irqsave(pll->lock, flags); in clk_pll_set_rate()
827 if (pll->params->flags & TEGRA_PLL_VCO_OUT) in clk_pll_set_rate()
834 if (pll->lock) in clk_pll_set_rate()
835 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_set_rate()
846 if (pll->params->flags & TEGRA_PLL_FIXED) { in clk_pll_round_rate()
848 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) in clk_pll_round_rate()
850 return pll->params->fixed_rate; in clk_pll_round_rate()
854 pll->params->calc_rate(hw, &cfg, rate, *prate)) in clk_pll_round_rate()
855 return -EINVAL; in clk_pll_round_rate()
871 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) in clk_pll_recalc_rate()
874 if ((pll->params->flags & TEGRA_PLL_FIXED) && in clk_pll_recalc_rate()
875 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in clk_pll_recalc_rate()
877 struct tegra_clk_pll_freq_table sel; in clk_pll_recalc_rate() local
878 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, in clk_pll_recalc_rate()
884 return pll->params->fixed_rate; in clk_pll_recalc_rate()
889 if (pll->params->flags & TEGRA_PLL_VCO_OUT) { in clk_pll_recalc_rate()
900 if (pll->params->set_gain) in clk_pll_recalc_rate()
901 pll->params->set_gain(&cfg); in clk_pll_recalc_rate()
916 if (!pll->pmc) in clk_plle_training()
917 return -ENOSYS; in clk_plle_training()
923 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
925 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
927 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
929 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
931 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
933 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
944 return -EBUSY; in clk_plle_training()
955 struct tegra_clk_pll_freq_table sel; in clk_plle_enable() local
965 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()
966 return -EINVAL; in clk_plle_enable()
981 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { in clk_plle_enable()
987 val |= sel.m << divm_shift(pll); in clk_plle_enable()
988 val |= sel.n << divn_shift(pll); in clk_plle_enable()
989 val |= sel.p << divp_shift(pll); in clk_plle_enable()
990 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; in clk_plle_enable()
999 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1002 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1021 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); in clk_plle_recalc_rate()
1022 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); in clk_plle_recalc_rate()
1023 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); in clk_plle_recalc_rate()
1041 if (pll->params->set_defaults) in tegra_clk_pll_restore_context()
1042 pll->params->set_defaults(pll); in tegra_clk_pll_restore_context()
1046 if (!__clk_get_enable_count(hw->clk)) in tegra_clk_pll_restore_context()
1126 return -EINVAL; in clk_pllu_enable()
1131 if (pll->lock) in clk_pllu_enable()
1132 spin_lock_irqsave(pll->lock, flags); in clk_pllu_enable()
1150 ret = -EINVAL; in clk_pllu_enable()
1158 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1161 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count); in clk_pllu_enable()
1163 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count); in clk_pllu_enable()
1168 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1170 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1173 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); in clk_pllu_enable()
1175 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count); in clk_pllu_enable()
1180 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1183 if (pll->lock) in clk_pllu_enable()
1184 spin_unlock_irqrestore(pll->lock, flags); in clk_pllu_enable()
1201 u16 mdiv = parent_rate / pll_params->cf_min; in _pll_fixed_mdiv()
1203 if (pll_params->flags & TEGRA_MDIV_NEW) in _pll_fixed_mdiv()
1204 return (!pll_params->mdiv_default ? mdiv : in _pll_fixed_mdiv()
1205 min(mdiv, pll_params->mdiv_default)); in _pll_fixed_mdiv()
1207 if (pll_params->mdiv_default) in _pll_fixed_mdiv()
1208 return pll_params->mdiv_default; in _pll_fixed_mdiv()
1210 if (parent_rate > pll_params->cf_max) in _pll_fixed_mdiv()
1225 return -EINVAL; in _calc_dynamic_ramp_rate()
1227 p = DIV_ROUND_UP(pll->params->vco_min, rate); in _calc_dynamic_ramp_rate()
1228 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); in _calc_dynamic_ramp_rate()
1229 cfg->output_rate = rate * p; in _calc_dynamic_ramp_rate()
1230 cfg->n = cfg->output_rate * cfg->m / parent_rate; in _calc_dynamic_ramp_rate()
1231 cfg->input_rate = parent_rate; in _calc_dynamic_ramp_rate()
1237 cfg->p = p_div; in _calc_dynamic_ramp_rate()
1239 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) in _calc_dynamic_ramp_rate()
1240 return -EINVAL; in _calc_dynamic_ramp_rate()
1254 return (u16)_pll_fixed_mdiv(pll->params, input_rate); in tegra_pll_get_fixed_mdiv()
1289 return -EINVAL; in _setup_dynamic_ramp()
1292 val = step_a << pll_params->stepa_shift; in _setup_dynamic_ramp()
1293 val |= step_b << pll_params->stepb_shift; in _setup_dynamic_ramp()
1294 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); in _setup_dynamic_ramp()
1310 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { in _pll_ramp_calc_pll()
1312 err = -EINVAL; in _pll_ramp_calc_pll()
1317 if (cfg->p > pll->params->max_p) in _pll_ramp_calc_pll()
1318 err = -EINVAL; in _pll_ramp_calc_pll()
1336 if (pll->lock) in clk_pllxc_set_rate()
1337 spin_lock_irqsave(pll->lock, flags); in clk_pllxc_set_rate()
1340 if (pll->params->flags & TEGRA_PLL_VCO_OUT) in clk_pllxc_set_rate()
1346 if (pll->lock) in clk_pllxc_set_rate()
1347 spin_unlock_irqrestore(pll->lock, flags); in clk_pllxc_set_rate()
1368 if (pll->params->set_gain) in clk_pll_ramp_round_rate()
1369 pll->params->set_gain(&cfg); in clk_pll_ramp_round_rate()
1400 if (pll->lock) in clk_pllc_enable()
1401 spin_lock_irqsave(pll->lock, flags); in clk_pllc_enable()
1415 if (pll->lock) in clk_pllc_enable()
1416 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_enable()
1439 if (pll->lock) in clk_pllc_disable()
1440 spin_lock_irqsave(pll->lock, flags); in clk_pllc_disable()
1444 if (pll->lock) in clk_pllc_disable()
1445 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_disable()
1470 return -EINVAL; in _pllcx_update_dynamic_coef()
1490 if (pll->lock) in clk_pllc_set_rate()
1491 spin_lock_irqsave(pll->lock, flags); in clk_pllc_set_rate()
1521 if (pll->lock) in clk_pllc_set_rate()
1522 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_set_rate()
1534 m = _pll_fixed_mdiv(pll->params, parent_rate); in _pllre_calc_rate()
1541 cfg->m = m; in _pllre_calc_rate()
1542 cfg->n = n; in _pllre_calc_rate()
1556 if (pll->lock) in clk_pllre_set_rate()
1557 spin_lock_irqsave(pll->lock, flags); in clk_pllre_set_rate()
1576 if (pll->lock) in clk_pllre_set_rate()
1577 spin_unlock_irqrestore(pll->lock, flags); in clk_pllre_set_rate()
1608 struct tegra_clk_pll_freq_table sel; in clk_plle_tegra114_enable() local
1616 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_tegra114_enable()
1617 return -EINVAL; in clk_plle_tegra114_enable()
1619 if (pll->lock) in clk_plle_tegra114_enable()
1620 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra114_enable()
1626 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1629 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1649 val |= sel.m << divm_shift(pll); in clk_plle_tegra114_enable()
1650 val |= sel.n << divn_shift(pll); in clk_plle_tegra114_enable()
1651 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; in clk_plle_tegra114_enable()
1678 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1681 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1684 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1710 if (pll->lock) in clk_plle_tegra114_enable()
1711 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra114_enable()
1722 if (pll->lock) in clk_plle_tegra114_disable()
1723 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra114_disable()
1732 if (pll->lock) in clk_plle_tegra114_disable()
1733 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra114_disable()
1748 return -EINVAL; in clk_pllu_tegra114_enable()
1756 if (pll->lock) in clk_pllu_tegra114_enable()
1757 spin_lock_irqsave(pll->lock, flags); in clk_pllu_tegra114_enable()
1775 ret = -EINVAL; in clk_pllu_tegra114_enable()
1783 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_tegra114_enable()
1786 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count); in clk_pllu_tegra114_enable()
1788 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count); in clk_pllu_tegra114_enable()
1793 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_tegra114_enable()
1795 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1798 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); in clk_pllu_tegra114_enable()
1800 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count); in clk_pllu_tegra114_enable()
1806 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1809 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1813 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1815 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1818 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1826 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1829 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1834 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1836 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1839 if (pll->lock) in clk_pllu_tegra114_enable()
1840 spin_unlock_irqrestore(pll->lock, flags); in clk_pllu_tegra114_enable()
1851 val_aux = pll_readl(pll->params->aux_reg, pll); in _clk_plle_tegra_init_parent()
1861 pll_writel(val_aux, pll->params->aux_reg, pll); in _clk_plle_tegra_init_parent()
1862 fence_udelay(1, pll->clk_base); in _clk_plle_tegra_init_parent()
1875 return ERR_PTR(-ENOMEM); in _tegra_init_pll()
1877 pll->clk_base = clk_base; in _tegra_init_pll()
1878 pll->pmc = pmc; in _tegra_init_pll()
1880 pll->params = pll_params; in _tegra_init_pll()
1881 pll->lock = lock; in _tegra_init_pll()
1883 if (!pll_params->div_nmp) in _tegra_init_pll()
1884 pll_params->div_nmp = &default_nmp; in _tegra_init_pll()
1902 if (!pll->params->calc_rate) { in _tegra_clk_register_pll()
1903 if (pll->params->flags & TEGRA_PLLM) in _tegra_clk_register_pll()
1904 pll->params->calc_rate = _calc_dynamic_ramp_rate; in _tegra_clk_register_pll()
1906 pll->params->calc_rate = _calc_rate; in _tegra_clk_register_pll()
1909 if (pll->params->set_defaults) in _tegra_clk_register_pll()
1910 pll->params->set_defaults(pll); in _tegra_clk_register_pll()
1913 pll->hw.init = &init; in _tegra_clk_register_pll()
1915 return clk_register(NULL, &pll->hw); in _tegra_clk_register_pll()
1926 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pll()
1957 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_plle()
1959 if (!pll_params->div_nmp) in tegra_clk_register_plle()
1960 pll_params->div_nmp = &pll_e_nmp; in tegra_clk_register_plle()
1981 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu()
2055 return ERR_PTR(-EINVAL); in tegra_clk_register_pllxc()
2058 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllxc()
2059 return ERR_PTR(-EINVAL); in tegra_clk_register_pllxc()
2063 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllxc()
2065 if (pll_params->adjust_vco) in tegra_clk_register_pllxc()
2066 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllxc()
2073 if (!pll_params->set_defaults) { in tegra_clk_register_pllxc()
2080 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllxc()
2081 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2084 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllxc()
2086 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllxc()
2088 clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2114 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre()
2116 if (pll_params->adjust_vco) in tegra_clk_register_pllre()
2117 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre()
2128 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & in tegra_clk_register_pllre()
2129 BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllre()
2135 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
2163 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllm()
2164 return ERR_PTR(-EINVAL); in tegra_clk_register_pllm()
2170 return ERR_PTR(-EINVAL); in tegra_clk_register_pllm()
2175 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllm()
2177 if (pll_params->adjust_vco) in tegra_clk_register_pllm()
2178 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllm()
2181 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllm()
2182 pll_params->flags |= TEGRA_PLLM; in tegra_clk_register_pllm()
2202 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc()
2208 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc()
2214 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc()
2219 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc()
2221 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc()
2236 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllc()
2238 while (p_tohw->pdiv) { in tegra_clk_register_pllc()
2239 if (p_tohw->pdiv == 2) { in tegra_clk_register_pllc()
2240 cfg.p = p_tohw->hw_val; in tegra_clk_register_pllc()
2246 if (!p_tohw->pdiv) { in tegra_clk_register_pllc()
2248 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc()
2255 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllc()
2256 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllc()
2257 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllc()
2301 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu_tegra114()
2339 if (!pll_params->div_nmp) in tegra_clk_register_pllss()
2340 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2346 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2359 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss()
2364 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllss()
2366 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) in tegra_clk_register_pllss()
2370 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2373 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; in tegra_clk_register_pllss()
2378 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllss()
2379 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllss()
2380 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllss()
2383 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2385 if (val_iddq & BIT(pll_params->iddq_bit_idx)) { in tegra_clk_register_pllss()
2388 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2391 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllss()
2392 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2418 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre_tegra210()
2420 if (pll_params->adjust_vco) in tegra_clk_register_pllre_tegra210()
2421 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre_tegra210()
2449 struct tegra_clk_pll_freq_table sel; in clk_plle_tegra210_enable() local
2460 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_tegra210_enable()
2461 return -EINVAL; in clk_plle_tegra210_enable()
2463 if (pll->lock) in clk_plle_tegra210_enable()
2464 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra210_enable()
2466 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2491 val |= sel.m << divm_shift(pll); in clk_plle_tegra210_enable()
2492 val |= sel.n << divn_shift(pll); in clk_plle_tegra210_enable()
2493 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; in clk_plle_tegra210_enable()
2522 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2525 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2528 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2531 if (pll->lock) in clk_plle_tegra210_enable()
2532 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra210_enable()
2543 if (pll->lock) in clk_plle_tegra210_disable()
2544 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra210_disable()
2547 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2555 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2557 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2565 if (pll->lock) in clk_plle_tegra210_disable()
2566 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra210_disable()
2614 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc_tegra210()
2619 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc_tegra210()
2625 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc_tegra210()
2630 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc_tegra210()
2632 if (pll_params->adjust_vco) in tegra_clk_register_pllc_tegra210()
2633 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllc_tegra210()
2636 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc_tegra210()
2660 if (!pll_params->div_nmp) in tegra_clk_register_pllss_tegra210()
2661 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss_tegra210()
2667 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss_tegra210()
2670 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllss_tegra210()
2673 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss_tegra210()
2678 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss_tegra210()
2680 if (pll_params->adjust_vco) in tegra_clk_register_pllss_tegra210()
2681 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllss_tegra210()
2684 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllss_tegra210()
2708 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllmb()
2709 return ERR_PTR(-EINVAL); in tegra_clk_register_pllmb()
2715 return ERR_PTR(-EINVAL); in tegra_clk_register_pllmb()
2720 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllmb()
2722 if (pll_params->adjust_vco) in tegra_clk_register_pllmb()
2723 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllmb()
2726 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllmb()
2727 pll_params->flags |= TEGRA_PLLMB; in tegra_clk_register_pllmb()