18 /* Macros to assist peripheral gate clock */
19 #define read_enb(gate) \  argument
20 	readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
21 #define write_enb_set(val, gate) \  argument
22 	writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
23 #define write_enb_clr(val, gate) \  argument
24 	writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
26 #define read_rst(gate) \  argument
27 	readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
28 #define write_rst_clr(val, gate) \  argument
29 	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
31 #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))  argument
35 /* Peripheral gate clock ops */
38 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);  in clk_periph_is_enabled()  local
41 	if (!(read_enb(gate) & periph_clk_to_bit(gate)))  in clk_periph_is_enabled()
44 	if (!(gate->flags & TEGRA_PERIPH_NO_RESET))  in clk_periph_is_enabled()
45 		if (read_rst(gate) & periph_clk_to_bit(gate))  in clk_periph_is_enabled()
53 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);  in clk_periph_enable()  local
58 	gate->enable_refcnt[gate->clk_num]++;  in clk_periph_enable()
59 	if (gate->enable_refcnt[gate->clk_num] > 1) {  in clk_periph_enable()
64 	write_enb_set(periph_clk_to_bit(gate), gate);  in clk_periph_enable()
67 	if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&  in clk_periph_enable()
68 	    !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {  in clk_periph_enable()
69 		if (read_rst(gate) & periph_clk_to_bit(gate)) {  in clk_periph_enable()
71 			write_rst_clr(periph_clk_to_bit(gate), gate);  in clk_periph_enable()
75 	if (gate->flags & TEGRA_PERIPH_WAR_1005168) {  in clk_periph_enable()
76 		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);  in clk_periph_enable()
77 		writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);  in clk_periph_enable()
79 		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);  in clk_periph_enable()
89 	struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);  in clk_periph_disable()  local
94 	gate->enable_refcnt[gate->clk_num]--;  in clk_periph_disable()
95 	if (gate->enable_refcnt[gate->clk_num] > 0) {  in clk_periph_disable()
105 	if (gate->flags & TEGRA_PERIPH_ON_APB)  in clk_periph_disable()
108 	write_enb_clr(periph_clk_to_bit(gate), gate);  in clk_periph_disable()
123 	struct tegra_clk_periph_gate *gate;  in tegra_clk_register_periph_gate()  local
132 	gate = kzalloc(sizeof(*gate), GFP_KERNEL);  in tegra_clk_register_periph_gate()
133 	if (!gate) {  in tegra_clk_register_periph_gate()
134 		pr_err("%s: could not allocate periph gate clk\n", __func__);  in tegra_clk_register_periph_gate()
144 	gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;  in tegra_clk_register_periph_gate()
145 	gate->clk_base = clk_base;  in tegra_clk_register_periph_gate()
146 	gate->clk_num = clk_num;  in tegra_clk_register_periph_gate()
147 	gate->flags = gate_flags;  in tegra_clk_register_periph_gate()
148 	gate->enable_refcnt = enable_refcnt;  in tegra_clk_register_periph_gate()
149 	gate->regs = pregs;  in tegra_clk_register_periph_gate()
151 	if (read_enb(gate) & periph_clk_to_bit(gate))  in tegra_clk_register_periph_gate()
155 	gate->hw.init = &init;  in tegra_clk_register_periph_gate()
157 	clk = clk_register(NULL, &gate->hw);  in tegra_clk_register_periph_gate()
159 		kfree(gate);  in tegra_clk_register_periph_gate()