1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2015 Chen-Yu Tsai
5  * Chen-Yu Tsai <wens@csie.org>
12 #include <linux/clk-provider.h>
22  * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
29 #define SUN9I_CPUS_MUX_GET_PARENT(reg)	((reg & SUN9I_CPUS_MUX_MASK) >> \  argument
34 #define SUN9I_CPUS_DIV_GET(reg)		((reg & SUN9I_CPUS_DIV_MASK) >> \  argument
36 #define SUN9I_CPUS_DIV_SET(reg, div)	((reg & ~SUN9I_CPUS_DIV_MASK) | \  argument
40 #define SUN9I_CPUS_PLL4_DIV_GET(reg)	((reg & SUN9I_CPUS_PLL4_DIV_MASK) >> \  argument
42 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \  argument
47 	void __iomem *reg;  member
57 	u32 reg;  in sun9i_a80_cpus_clk_recalc_rate()  local
60 	reg = readl(cpus->reg);  in sun9i_a80_cpus_clk_recalc_rate()
62 	/* apply pre-divider first if parent is pll4 */  in sun9i_a80_cpus_clk_recalc_rate()
63 	if (SUN9I_CPUS_MUX_GET_PARENT(reg) == SUN9I_CPUS_MUX_PARENT_PLL4)  in sun9i_a80_cpus_clk_recalc_rate()
64 		parent_rate /= SUN9I_CPUS_PLL4_DIV_GET(reg) + 1;  in sun9i_a80_cpus_clk_recalc_rate()
67 	rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1);  in sun9i_a80_cpus_clk_recalc_rate()
86 	/* calculate pre-divider if parent is pll4 */  in sun9i_a80_cpus_clk_round()
88 		/* pre-divider is 1 ~ 32 */  in sun9i_a80_cpus_clk_round()
106 		*divp = div - 1;  in sun9i_a80_cpus_clk_round()
107 		*pre_divp = pre_div - 1;  in sun9i_a80_cpus_clk_round()
119 	unsigned long rate = req->rate;  in sun9i_a80_cpus_clk_determine_rate()
143 		return -EINVAL;  in sun9i_a80_cpus_clk_determine_rate()
145 	req->best_parent_hw = best_parent;  in sun9i_a80_cpus_clk_determine_rate()
146 	req->best_parent_rate = best;  in sun9i_a80_cpus_clk_determine_rate()
147 	req->rate = best_child_rate;  in sun9i_a80_cpus_clk_determine_rate()
158 	u32 reg;  in sun9i_a80_cpus_clk_set_rate()  local
162 	reg = readl(cpus->reg);  in sun9i_a80_cpus_clk_set_rate()
164 	/* need to know which parent is used to apply pre-divider */  in sun9i_a80_cpus_clk_set_rate()
165 	parent = SUN9I_CPUS_MUX_GET_PARENT(reg);  in sun9i_a80_cpus_clk_set_rate()
168 	reg = SUN9I_CPUS_DIV_SET(reg, div);  in sun9i_a80_cpus_clk_set_rate()
169 	reg = SUN9I_CPUS_PLL4_DIV_SET(reg, pre_div);  in sun9i_a80_cpus_clk_set_rate()
170 	writel(reg, cpus->reg);  in sun9i_a80_cpus_clk_set_rate()
185 	const char *clk_name = node->name;  in sun9i_a80_cpus_setup()
197 	cpus->reg = of_io_request_and_map(node, 0, of_node_full_name(node));  in sun9i_a80_cpus_setup()
198 	if (IS_ERR(cpus->reg))  in sun9i_a80_cpus_setup()
201 	of_property_read_string(node, "clock-output-names", &clk_name);  in sun9i_a80_cpus_setup()
211 	mux->reg = cpus->reg;  in sun9i_a80_cpus_setup()
212 	mux->shift = SUN9I_CPUS_MUX_SHIFT;  in sun9i_a80_cpus_setup()
213 	/* un-shifted mask is what mux_clk expects */  in sun9i_a80_cpus_setup()
214 	mux->mask = SUN9I_CPUS_MUX_MASK >> SUN9I_CPUS_MUX_SHIFT;  in sun9i_a80_cpus_setup()
215 	mux->lock = &sun9i_a80_cpus_lock;  in sun9i_a80_cpus_setup()
218 				     &mux->hw, &clk_mux_ops,  in sun9i_a80_cpus_setup()
219 				     &cpus->hw, &sun9i_a80_cpus_clk_ops,  in sun9i_a80_cpus_setup()
235 	iounmap(cpus->reg);  in sun9i_a80_cpus_setup()
241 CLK_OF_DECLARE(sun9i_a80_cpus, "allwinner,sun9i-a80-cpus-clk",