175 	struct mmc_phase *phase = to_mmc_phase(hw);  in mmc_get_phase()  local
181 	value = readl(phase->reg);  in mmc_get_phase()
182 	delay = (value >> phase->offset) & 0x3;  in mmc_get_phase()
217 	struct mmc_phase *phase = to_mmc_phase(hw);  in mmc_set_phase()  local
268 	spin_lock_irqsave(phase->lock, flags);  in mmc_set_phase()
269 	value = readl(phase->reg);  in mmc_set_phase()
270 	value &= ~GENMASK(phase->offset + 3, phase->offset);  in mmc_set_phase()
271 	value |= delay << phase->offset;  in mmc_set_phase()
272 	writel(value, phase->reg);  in mmc_set_phase()
273 	spin_unlock_irqrestore(phase->lock, flags);  in mmc_set_phase()
288  * through struct factors_data. The phase clocks parts are identical.
326 		struct mmc_phase *phase;  in sunxi_mmc_setup()  local
328 		phase = kmalloc(sizeof(*phase), GFP_KERNEL);  in sunxi_mmc_setup()
329 		if (!phase)  in sunxi_mmc_setup()
332 		phase->hw.init = &init;  in sunxi_mmc_setup()
333 		phase->reg = reg;  in sunxi_mmc_setup()
334 		phase->lock = lock;  in sunxi_mmc_setup()
337 			phase->offset = 8;  in sunxi_mmc_setup()
339 			phase->offset = 20;  in sunxi_mmc_setup()
345 		clk_data->clks[i] = clk_register(NULL, &phase->hw);  in sunxi_mmc_setup()
347 			kfree(phase);  in sunxi_mmc_setup()