Lines Matching +full:0 +full:x18c

28 	{ .index = 3, .shift = 0, .width = 5 },
43 		.reg		= 0x000,
48 						      0),
52 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
54 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
68 		.reg		= 0x010,
73 						      0),
85 		      0x11c, BIT(0), 0);
87 		      0x12c, BIT(0), 0);
89 		      0x13c, BIT(0), 0);
91 		      0x18c, BIT(0), 0);
93 		      0x19c, BIT(0), 0);
95 		      0x1cc, BIT(0), 0);
97 		      0x1ec, BIT(0), 0);
102 				  r_mod0_default_parents, 0x1c0,
103 				  0, 5,		/* M */
107 				  0);
117 				  r_mod0_default_parents, 0x1e0,
118 				  0, 5,		/* M */
122 				  0);
159 	[RST_R_APB1_TIMER]	=  { 0x11c, BIT(16) },
160 	[RST_R_APB1_TWD]	=  { 0x12c, BIT(16) },
161 	[RST_R_APB1_PWM]	=  { 0x13c, BIT(16) },
162 	[RST_R_APB2_UART]	=  { 0x18c, BIT(16) },
163 	[RST_R_APB2_I2C]	=  { 0x19c, BIT(16) },
164 	[RST_R_APB1_IR]		=  { 0x1cc, BIT(16) },
165 	[RST_R_APB1_W1]		=  { 0x1ec, BIT(16) },
183 	reg = of_io_request_and_map(node, 0, of_node_full_name(node));  in sunxi_r_ccu_init()