Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
24 #include "ccu-sun50i-a100.h"
26 #define SUN50I_A100_PLL_SDM_ENABLE BIT(24)
27 #define SUN50I_A100_PLL_OUTPUT_ENABLE BIT(27)
28 #define SUN50I_A100_PLL_LOCK BIT(28)
29 #define SUN50I_A100_PLL_LOCK_ENABLE BIT(29)
30 #define SUN50I_A100_PLL_ENABLE BIT(31)
51 .hw.init = CLK_HW_INIT("pll-cpux", "dcxo24M",
67 .hw.init = CLK_HW_INIT("pll-ddr0", "dcxo24M",
85 .hw.init = CLK_HW_INIT("pll-periph0", "dcxo24M",
102 .hw.init = CLK_HW_INIT("pll-periph1", "dcxo24M",
118 .hw.init = CLK_HW_INIT("pll-gpu", "dcxo24M",
138 .hw.init = CLK_HW_INIT("pll-video0", "dcxo24M",
154 .hw.init = CLK_HW_INIT("pll-video1", "dcxo24M",
170 .hw.init = CLK_HW_INIT("pll-video2", "dcxo24M",
185 .hw.init = CLK_HW_INIT("pll-ve", "dcxo24M",
206 .sdm = _SUNXI_CCU_SDM(pll_com_sdm_table, BIT(24),
207 0x160, BIT(31)),
211 .hw.init = CLK_HW_INIT("pll-com", "dcxo24M",
227 .hw.init = CLK_HW_INIT("pll-video3", "dcxo24M",
253 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
254 0x178, BIT(31)),
259 .hw.init = CLK_HW_INIT("pll-audio", "dcxo24M",
266 "iosc", "pll-cpux",
267 "pll-periph0" };
269 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
271 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
274 "iosc", "pll-periph0",
275 "pll-periph0-2x" };
276 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
280 24, 3, /* mux */
284 "psi-ahb1-ahb2",
285 "pll-periph0",
286 "pll-periph0-2x" };
290 24, 3, /* mux */
296 24, 3, /* mux */
302 24, 3, /* mux */
305 static const char * const mbus_parents[] = { "dcxo24M", "pll-ddr0",
306 "pll-periph0",
307 "pll-periph0-2x" };
310 24, 2, /* mux */
311 BIT(31), /* gate */
314 static const char * const de_parents[] = { "pll-com", "pll-periph0-2x" };
317 24, 1, /* mux */
318 BIT(31), /* gate */
321 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
322 0x60c, BIT(0), 0);
324 static const char * const g2d_parents[] = { "pll-com", "pll-periph0-2x",
325 "pll-video0-2x", "pll-video1-2x",
326 "pll-video2-2x"};
331 24, 3, /* mux */
332 BIT(31), /* gate */
335 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
336 0x63c, BIT(0), 0);
338 static const char * const gpu_parents[] = { "pll-gpu" };
341 24, 1, /* mux */
342 BIT(31), /* gate */
345 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
346 0x67c, BIT(0), 0);
348 static const char * const ce_parents[] = { "dcxo24M", "pll-periph0-2x" };
352 24, 1, /* mux */
353 BIT(31), /* gate */
356 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
357 0x68c, BIT(0), 0);
359 static const char * const ve_parents[] = { "pll-ve" };
362 24, 1, /* mux */
363 BIT(31), /* gate */
366 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
367 0x69c, BIT(0), 0);
369 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
370 0x70c, BIT(0), 0);
372 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
373 0x71c, BIT(0), 0);
375 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
376 0x72c, BIT(0), 0);
378 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
379 0x73c, BIT(0), 0);
381 static SUNXI_CCU_GATE(avs_clk, "avs", "dcxo24M", 0x740, BIT(31), 0);
383 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
384 0x78c, BIT(0), 0);
386 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
387 0x79c, BIT(0), 0);
389 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
391 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
393 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
394 0x804, BIT(0), 0);
395 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
396 0x804, BIT(1), 0);
397 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
398 0x804, BIT(2), 0);
399 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
400 0x804, BIT(5), 0);
401 static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
402 0x804, BIT(8), 0);
403 static SUNXI_CCU_GATE(mbus_isp_clk, "mbus-isp", "mbus",
404 0x804, BIT(9), 0);
405 static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
406 0x804, BIT(10), 0);
408 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
409 0x80c, BIT(0), CLK_IS_CRITICAL);
412 "pll-periph0",
413 "pll-periph1",
414 "pll-periph0-2x",
415 "pll-periph1-2x" };
419 24, 3, /* mux */
420 BIT(31), /* gate */
426 24, 3, /* mux */
427 BIT(31), /* gate */
430 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
432 static const char * const mmc_parents[] = { "dcxo24M", "pll-periph0-2x",
433 "pll-periph1-2x" };
437 24, 2, /* mux */
438 BIT(31), /* gate */
439 2, /* post-div */
445 24, 2, /* mux */
446 BIT(31), /* gate */
447 2, /* post-div */
453 24, 2, /* mux */
454 BIT(31), /* gate */
455 2, /* post-div */
458 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
459 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
460 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
462 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
463 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
464 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
465 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
466 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
468 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
469 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
470 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
471 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
476 24, 3, /* mux */
477 BIT(31), /* gate */
483 24, 3, /* mux */
484 BIT(31), /* gate */
490 24, 3, /* mux */
491 BIT(31), /* gate */
494 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
495 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
496 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb3", 0x96c, BIT(2), 0);
498 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
499 BIT(31) | BIT(30), 0);
501 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
504 "pll-periph0", "pll-periph1" };
505 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_parents, 0x990,
508 24, 3, /* mux */
509 BIT(31), /* gate */
512 static SUNXI_CCU_GATE(bus_ir_rx_clk, "bus-ir-rx", "ahb3", 0x99c, BIT(0), 0);
514 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_parents, 0x9c0,
517 24, 3, /* mux */
518 BIT(31), /* gate */
521 static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
523 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
525 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
527 static const char * const audio_parents[] = { "pll-audio", "pll-com-audio" };
529 .enable = BIT(31),
531 .mux = _SUNXI_CCU_MUX(24, 2),
542 .enable = BIT(31),
544 .mux = _SUNXI_CCU_MUX(24, 2),
555 .enable = BIT(31),
557 .mux = _SUNXI_CCU_MUX(24, 2),
568 .enable = BIT(31),
570 .mux = _SUNXI_CCU_MUX(24, 2),
580 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa20, BIT(0), 0);
581 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa20, BIT(1), 0);
582 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa20, BIT(2), 0);
583 static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa20, BIT(3), 0);
586 .enable = BIT(31),
588 .mux = _SUNXI_CCU_MUX(24, 2),
598 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
601 .enable = BIT(31),
603 .mux = _SUNXI_CCU_MUX(24, 2),
613 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
615 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_dac_clk, "audio-codec-dac",
618 24, 2, /* mux */
619 BIT(31), /* gate */
622 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_adc_clk, "audio-codec-adc",
625 24, 2, /* mux */
626 BIT(31), /* gate */
629 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
632 24, 2, /* mux */
633 BIT(31), /* gate */
636 static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
637 BIT(0), 0);
646 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
647 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "dcxo24M", 0xa70, BIT(29), 0);
649 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
650 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "dcxo24M", 0xa74, BIT(29), 0);
652 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
653 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
654 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
655 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
656 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
658 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "ahb3", 0xa9c, BIT(0), 0);
660 static SUNXI_CCU_GATE(bus_dpss_top0_clk, "bus-dpss-top0", "ahb3",
661 0xabc, BIT(0), 0);
663 static SUNXI_CCU_GATE(bus_dpss_top1_clk, "bus-dpss-top1", "ahb3",
664 0xacc, BIT(0), 0);
666 static const char * const mipi_dsi_parents[] = { "dcxo24M", "pll-periph0-2x",
667 "pll-periph0" };
668 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi",
672 24, 2, /* mux */
673 BIT(31), /* gate */
676 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb3",
677 0xb4c, BIT(0), 0);
679 static const char * const tcon_lcd_parents[] = { "pll-video0-4x",
680 "pll-video1-4x",
681 "pll-video2-4x",
682 "pll-video3-4x",
683 "pll-periph0-2x" };
684 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_lcd_clk, "tcon-lcd0",
688 24, 3, /* mux */
689 BIT(31), /* gate */
692 static SUNXI_CCU_GATE(bus_tcon_lcd_clk, "bus-tcon-lcd0", "ahb3",
693 0xb7c, BIT(0), 0);
696 "pll-periph0" };
701 24, 3, /* mux */
702 BIT(31), /* gate */
705 static SUNXI_CCU_GATE(bus_ledc_clk, "bus-ledc", "ahb3", 0xbfc, BIT(0), 0);
707 static const char * const csi_top_parents[] = { "pll-periph0-2x",
708 "pll-video0-2x",
709 "pll-video1-2x",
710 "pll-video2-2x",
711 "pll-video3-2x" };
712 static SUNXI_CCU_M_WITH_MUX_GATE(csi_top_clk, "csi-top",
715 24, 3, /* mux */
716 BIT(31), /* gate */
719 static const char * const csi0_mclk_parents[] = { "dcxo24M", "pll-video2",
720 "pll-video3", "pll-video0",
721 "pll-video1" };
722 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk",
725 24, 3, /* mux */
726 BIT(31), /* gate */
729 static const char * const csi1_mclk_parents[] = { "dcxo24M", "pll-video3",
730 "pll-video0", "pll-video1",
731 "pll-video2" };
732 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk",
735 24, 3, /* mux */
736 BIT(31), /* gate */
739 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc1c, BIT(0), 0);
741 static const char * const csi_isp_parents[] = { "pll-periph0-2x",
742 "pll-video0-2x",
743 "pll-video1-2x",
744 "pll-video2-2x",
745 "pll-video3-2x" };
746 static SUNXI_CCU_M_WITH_MUX_GATE(csi_isp_clk, "csi-isp",
749 24, 3, /* mux */
750 BIT(31), /* gate */
756 static CLK_FIXED_FACTOR_HW(pll_com_audio_clk, "pll-com-audio",
760 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
764 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
771 static CLK_FIXED_FACTOR_HWS(pll_video0_4x_clk, "pll-video0-4x",
774 static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x",
781 static CLK_FIXED_FACTOR_HWS(pll_video1_4x_clk, "pll-video1-4x",
784 static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x",
791 static CLK_FIXED_FACTOR_HWS(pll_video2_4x_clk, "pll-video2-4x",
794 static CLK_FIXED_FACTOR_HWS(pll_video2_2x_clk, "pll-video2-2x",
801 static CLK_FIXED_FACTOR_HWS(pll_video3_4x_clk, "pll-video3-4x",
804 static CLK_FIXED_FACTOR_HWS(pll_video3_2x_clk, "pll-video3-2x",
1066 [RST_MBUS] = { 0x540, BIT(30) },
1068 [RST_BUS_DE] = { 0x60c, BIT(16) },
1069 [RST_BUS_G2D] = { 0x63c, BIT(16) },
1070 [RST_BUS_GPU] = { 0x67c, BIT(16) },
1071 [RST_BUS_CE] = { 0x68c, BIT(16) },
1072 [RST_BUS_VE] = { 0x69c, BIT(16) },
1073 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1074 [RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
1075 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1076 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
1077 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1078 [RST_BUS_PSI] = { 0x79c, BIT(16) },
1079 [RST_BUS_PWM] = { 0x7ac, BIT(16) },
1080 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1081 [RST_BUS_NAND] = { 0x82c, BIT(16) },
1082 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1083 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1084 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1085 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1086 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1087 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1088 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1089 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1090 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1091 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1092 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1093 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1094 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1095 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1096 [RST_BUS_SPI2] = { 0x96c, BIT(18) },
1097 [RST_BUS_EMAC] = { 0x97c, BIT(16) },
1098 [RST_BUS_IR_RX] = { 0x99c, BIT(16) },
1099 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1100 [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
1101 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1102 [RST_BUS_I2S0] = { 0xa20, BIT(16) },
1103 [RST_BUS_I2S1] = { 0xa20, BIT(17) },
1104 [RST_BUS_I2S2] = { 0xa20, BIT(18) },
1105 [RST_BUS_I2S3] = { 0xa20, BIT(19) },
1106 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1107 [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1108 [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
1110 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1111 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1113 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1114 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1115 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1116 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1117 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1119 [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
1120 [RST_BUS_DPSS_TOP0] = { 0xabc, BIT(16) },
1121 [RST_BUS_DPSS_TOP1] = { 0xacc, BIT(16) },
1122 [RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
1123 [RST_BUS_TCON_LCD] = { 0xb7c, BIT(16) },
1124 [RST_BUS_LVDS] = { 0xbac, BIT(16) },
1125 [RST_BUS_LEDC] = { 0xbfc, BIT(16) },
1126 [RST_BUS_CSI] = { 0xc1c, BIT(16) },
1127 [RST_BUS_CSI_ISP] = { 0xc2c, BIT(16) },
1170 .enable = BIT(27),
1171 .lock = BIT(28),
1220 * See the comment before pll-video0 definition for the reason. in sun50i_a100_ccu_probe()
1224 val &= ~BIT(0); in sun50i_a100_ccu_probe()
1231 * See the comment before pll-audio definition for the reason. in sun50i_a100_ccu_probe()
1234 val &= ~BIT(1); in sun50i_a100_ccu_probe()
1235 val |= BIT(0); in sun50i_a100_ccu_probe()
1246 val &= ~GENMASK(25, 24); in sun50i_a100_ccu_probe()
1250 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a100_ccu_desc); in sun50i_a100_ccu_probe()
1265 { .compatible = "allwinner,sun50i-a100-ccu" },
1272 .name = "sun50i-a100-ccu",