Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/clk-provider.h>
127 * prepare - clk_(un)prepare only ensures parent is (un)prepared
128 * enable - clk_enable/disable only ensures parent is enabled
129 * rate - rate is fixed. No clk_set_rate support
130 * parent - fixed parent. No clk_set_parent support
137 * @hw: handle between common and hardware-specific interfaces.
184 void __iomem *base = pll->regs_base; in __clkgen_pll_enable()
185 struct clkgen_field *field = &pll->data->locked_status; in __clkgen_pll_enable()
187 u32 reg; in __clkgen_pll_enable() local
194 ret = readl_relaxed_poll_timeout(base + field->offset, reg, in __clkgen_pll_enable()
195 !!((reg >> field->shift) & field->mask), 0, 10000); in __clkgen_pll_enable()
198 if (pll->data->switch2pll_en) in __clkgen_pll_enable()
201 pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__); in __clkgen_pll_enable()
213 if (pll->lock) in clkgen_pll_enable()
214 spin_lock_irqsave(pll->lock, flags); in clkgen_pll_enable()
218 if (pll->lock) in clkgen_pll_enable()
219 spin_unlock_irqrestore(pll->lock, flags); in clkgen_pll_enable()
231 if (pll->data->switch2pll_en) in __clkgen_pll_disable()
236 pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__); in __clkgen_pll_disable()
244 if (pll->lock) in clkgen_pll_disable()
245 spin_lock_irqsave(pll->lock, flags); in clkgen_pll_disable()
249 if (pll->lock) in clkgen_pll_disable()
250 spin_unlock_irqrestore(pll->lock, flags); in clkgen_pll_disable()
268 return -EINVAL; in clk_pll3200c32_get_params()
284 new_deviation = abs(new_freq - output); in clk_pll3200c32_get_params()
287 pll->idf = i; in clk_pll3200c32_get_params()
288 pll->ndiv = n; in clk_pll3200c32_get_params()
294 return -EINVAL; in clk_pll3200c32_get_params()
297 for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++) in clk_pll3200c32_get_params()
306 if (!pll->idf) in clk_pll3200c32_get_rate()
307 pll->idf = 1; in clk_pll3200c32_get_rate()
309 *rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000; in clk_pll3200c32_get_rate()
345 __clk_get_name(hw->clk), rate); in round_rate_stm_pll3200c32()
350 __func__, __clk_get_name(hw->clk), in round_rate_stm_pll3200c32()
366 return -EINVAL; in set_rate_stm_pll3200c32()
372 __func__, __clk_get_name(hw->clk), in set_rate_stm_pll3200c32()
377 return -EINVAL; in set_rate_stm_pll3200c32()
379 pll->ndiv = params.ndiv; in set_rate_stm_pll3200c32()
380 pll->idf = params.idf; in set_rate_stm_pll3200c32()
381 pll->cp = params.cp; in set_rate_stm_pll3200c32()
385 if (pll->lock) in set_rate_stm_pll3200c32()
386 spin_lock_irqsave(pll->lock, flags); in set_rate_stm_pll3200c32()
388 CLKGEN_WRITE(pll, ndiv, pll->ndiv); in set_rate_stm_pll3200c32()
389 CLKGEN_WRITE(pll, idf, pll->idf); in set_rate_stm_pll3200c32()
390 CLKGEN_WRITE(pll, cp, pll->cp); in set_rate_stm_pll3200c32()
392 if (pll->lock) in set_rate_stm_pll3200c32()
393 spin_unlock_irqrestore(pll->lock, flags); in set_rate_stm_pll3200c32()
424 return -EINVAL; in clk_pll4600c28_get_params()
439 for (; n >= 8 && deviation; n--) { in clk_pll4600c28_get_params()
444 new_deviation = new_freq - output; in clk_pll4600c28_get_params()
446 pll->idf = i; in clk_pll4600c28_get_params()
447 pll->ndiv = n; in clk_pll4600c28_get_params()
454 return -EINVAL; in clk_pll4600c28_get_params()
462 if (!pll->idf) in clk_pll4600c28_get_rate()
463 pll->idf = 1; in clk_pll4600c28_get_rate()
465 *rate = (input / pll->idf) * 2 * pll->ndiv; in clk_pll4600c28_get_rate()
485 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); in recalc_stm_pll4600c28()
499 __clk_get_name(hw->clk), rate); in round_rate_stm_pll4600c28()
504 __func__, __clk_get_name(hw->clk), in round_rate_stm_pll4600c28()
520 return -EINVAL; in set_rate_stm_pll4600c28()
526 __clk_get_name(hw->clk), rate); in set_rate_stm_pll4600c28()
527 return -EINVAL; in set_rate_stm_pll4600c28()
531 __func__, __clk_get_name(hw->clk), in set_rate_stm_pll4600c28()
536 return -EINVAL; in set_rate_stm_pll4600c28()
538 pll->ndiv = params.ndiv; in set_rate_stm_pll4600c28()
539 pll->idf = params.idf; in set_rate_stm_pll4600c28()
543 if (pll->lock) in set_rate_stm_pll4600c28()
544 spin_lock_irqsave(pll->lock, flags); in set_rate_stm_pll4600c28()
546 CLKGEN_WRITE(pll, ndiv, pll->ndiv); in set_rate_stm_pll4600c28()
547 CLKGEN_WRITE(pll, idf, pll->idf); in set_rate_stm_pll4600c28()
549 if (pll->lock) in set_rate_stm_pll4600c28()
550 spin_unlock_irqrestore(pll->lock, flags); in set_rate_stm_pll4600c28()
584 void __iomem *reg, unsigned long pll_flags, in clkgen_pll_register() argument
593 return ERR_PTR(-ENOMEM); in clkgen_pll_register()
596 init.ops = pll_data->ops; in clkgen_pll_register()
602 pll->data = pll_data; in clkgen_pll_register()
603 pll->regs_base = reg; in clkgen_pll_register()
604 pll->hw.init = &init; in clkgen_pll_register()
605 pll->lock = lock; in clkgen_pll_register()
607 clk = clk_register(NULL, &pll->hw); in clkgen_pll_register()
625 void __iomem *reg = NULL; in clkgen_get_register_base() local
631 reg = of_iomap(pnode, 0); in clkgen_get_register_base()
634 return reg; in clkgen_get_register_base()
638 void __iomem *reg, in clkgen_odf_register() argument
653 return ERR_PTR(-ENOMEM); in clkgen_odf_register()
655 gate->flags = CLK_GATE_SET_TO_DISABLE; in clkgen_odf_register()
656 gate->reg = reg + pll_data->odf_gate[odf].offset; in clkgen_odf_register()
657 gate->bit_idx = pll_data->odf_gate[odf].shift; in clkgen_odf_register()
658 gate->lock = odf_lock; in clkgen_odf_register()
663 return ERR_PTR(-ENOMEM); in clkgen_odf_register()
666 div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; in clkgen_odf_register()
667 div->reg = reg + pll_data->odf[odf].offset; in clkgen_odf_register()
668 div->shift = pll_data->odf[odf].shift; in clkgen_odf_register()
669 div->width = fls(pll_data->odf[odf].mask); in clkgen_odf_register()
670 div->lock = odf_lock; in clkgen_odf_register()
674 &div->hw, &clk_divider_ops, in clkgen_odf_register()
675 &gate->hw, &clk_gate_ops, in clkgen_odf_register()
710 np->name, data->lock); in clkgen_c32_pll_setup()
716 num_odfs = data->num_odfs; in clkgen_c32_pll_setup()
722 clk_data->clk_num = num_odfs; in clkgen_c32_pll_setup()
723 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), in clkgen_c32_pll_setup()
726 if (!clk_data->clks) in clkgen_c32_pll_setup()
734 if (of_property_read_string_index(np, "clock-output-names", in clkgen_c32_pll_setup()
745 clk_data->clks[odf] = clk; in clkgen_c32_pll_setup()
753 kfree(clk_data->clks); in clkgen_c32_pll_setup()
761 CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
768 CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
775 CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
782 CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);