1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
163  * prepare - clk_(un)prepare only ensures parent is (un)prepared
164  * enable - clk_enable and clk_disable are functional & control the Fsyn
165  * rate - inherits rate from parent. set_rate/round_rate/recalc_rate
166  * parent - fixed parent.  No clk_set_parent support
170  * struct st_clk_quadfs_pll - A pll which outputs a fixed multiplier of
174  * @hw: handle between common and hardware-specific interfaces.
195 	if (pll->lock)  in quadfs_pll_enable()
196 		spin_lock_irqsave(pll->lock, flags);  in quadfs_pll_enable()
201 	if (pll->data->reset_present)  in quadfs_pll_enable()
207 	if (pll->data->bwfilter_present)  in quadfs_pll_enable()
211 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);  in quadfs_pll_enable()
216 	CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity);  in quadfs_pll_enable()
218 	if (pll->lock)  in quadfs_pll_enable()
219 		spin_unlock_irqrestore(pll->lock, flags);  in quadfs_pll_enable()
221 	if (pll->data->lockstatus_present)  in quadfs_pll_enable()
224 				return -ETIMEDOUT;  in quadfs_pll_enable()
236 	if (pll->lock)  in quadfs_pll_disable()
237 		spin_lock_irqsave(pll->lock, flags);  in quadfs_pll_disable()
243 	CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity);  in quadfs_pll_disable()
245 	if (pll->data->reset_present)  in quadfs_pll_disable()
248 	if (pll->lock)  in quadfs_pll_disable()
249 		spin_unlock_irqrestore(pll->lock, flags);  in quadfs_pll_disable()
257 	return pll->data->powerup_polarity ? !npda : !!npda;  in quadfs_pll_is_enabled()
263 	unsigned long nd = fs->ndiv + 16; /* ndiv value */  in clk_fs660c32_vco_get_rate()
282 	pll->ndiv = params.ndiv;  in quadfs_pll_fs660c32_recalc_rate()
298 		return -EINVAL;  in clk_fs660c32_vco_get_params()
303 		return -EINVAL;  in clk_fs660c32_vco_get_params()
311 	fs->ndiv = n - 16; /* Converting formula value to reg value */  in clk_fs660c32_vco_get_params()
344 		return -EINVAL;  in quadfs_pll_fs660c32_set_rate()
357 		return -EINVAL;  in quadfs_pll_fs660c32_set_rate()
359 	pll->ndiv = params.ndiv;  in quadfs_pll_fs660c32_set_rate()
361 	if (pll->lock)  in quadfs_pll_fs660c32_set_rate()
362 		spin_lock_irqsave(pll->lock, flags);  in quadfs_pll_fs660c32_set_rate()
364 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);  in quadfs_pll_fs660c32_set_rate()
366 	if (pll->lock)  in quadfs_pll_fs660c32_set_rate()
367 		spin_unlock_irqrestore(pll->lock, flags);  in quadfs_pll_fs660c32_set_rate()
383 		struct clkgen_quadfs_data *quadfs, void __iomem *reg,  in st_clk_register_quadfs_pll()  argument
394 		return ERR_PTR(-EINVAL);  in st_clk_register_quadfs_pll()
398 		return ERR_PTR(-ENOMEM);  in st_clk_register_quadfs_pll()
401 	init.ops = quadfs->pll_ops;  in st_clk_register_quadfs_pll()
406 	pll->data = quadfs;  in st_clk_register_quadfs_pll()
407 	pll->regs_base = reg;  in st_clk_register_quadfs_pll()
408 	pll->lock = lock;  in st_clk_register_quadfs_pll()
409 	pll->hw.init = &init;  in st_clk_register_quadfs_pll()
411 	clk = clk_register(NULL, &pll->hw);  in st_clk_register_quadfs_pll()
423  * prepare - clk_(un)prepare only ensures parent is (un)prepared
424  * enable - clk_enable and clk_disable are functional
425  * rate - set rate is functional
426  * parent - fixed parent.  No clk_set_parent support
430  * struct st_clk_quadfs_fsynth - One clock output from a four channel digital
433  * @hw: handle between common and hardware-specific interfaces
477 	CLKGEN_WRITE(fs, en[fs->chan], 1);  in quadfs_fsynth_program_enable()
478 	CLKGEN_WRITE(fs, en[fs->chan], 0);  in quadfs_fsynth_program_enable()
490 	CLKGEN_WRITE(fs, en[fs->chan], 0);  in quadfs_fsynth_program_rate()
492 	CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md);  in quadfs_fsynth_program_rate()
493 	CLKGEN_WRITE(fs, pe[fs->chan], fs->pe);  in quadfs_fsynth_program_rate()
494 	CLKGEN_WRITE(fs, sdiv[fs->chan], fs->sdiv);  in quadfs_fsynth_program_rate()
496 	if (fs->lock)  in quadfs_fsynth_program_rate()
497 		spin_lock_irqsave(fs->lock, flags);  in quadfs_fsynth_program_rate()
499 	if (fs->data->nsdiv_present)  in quadfs_fsynth_program_rate()
500 		CLKGEN_WRITE(fs, nsdiv[fs->chan], fs->nsdiv);  in quadfs_fsynth_program_rate()
502 	if (fs->lock)  in quadfs_fsynth_program_rate()
503 		spin_unlock_irqrestore(fs->lock, flags);  in quadfs_fsynth_program_rate()
515 	if (fs->lock)  in quadfs_fsynth_enable()
516 		spin_lock_irqsave(fs->lock, flags);  in quadfs_fsynth_enable()
518 	CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);  in quadfs_fsynth_enable()
520 	if (fs->data->nrst_present)  in quadfs_fsynth_enable()
521 		CLKGEN_WRITE(fs, nrst[fs->chan], 0);  in quadfs_fsynth_enable()
523 	if (fs->lock)  in quadfs_fsynth_enable()
524 		spin_unlock_irqrestore(fs->lock, flags);  in quadfs_fsynth_enable()
538 	if (fs->lock)  in quadfs_fsynth_disable()
539 		spin_lock_irqsave(fs->lock, flags);  in quadfs_fsynth_disable()
541 	CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity);  in quadfs_fsynth_disable()
543 	if (fs->lock)  in quadfs_fsynth_disable()
544 		spin_unlock_irqrestore(fs->lock, flags);  in quadfs_fsynth_disable()
550 	u32 nsb = CLKGEN_READ(fs, nsb[fs->chan]);  in quadfs_fsynth_is_enabled()
555 	return fs->data->standby_polarity ? !nsb : !!nsb;  in quadfs_fsynth_is_enabled()
563 	unsigned long s = (1 << fs->sdiv);  in clk_fs660c32_dig_get_rate()
575 	ns = (fs->nsdiv == 1) ? 1 : 3;  in clk_fs660c32_dig_get_rate()
577 	res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns;  in clk_fs660c32_dig_get_rate()
594 	*p = (uint64_t)input * P20 - (32LL  + (uint64_t)m) * val * (P20 / 32LL);  in clk_fs660c32_get_pe()
608 	new_deviation = abs(output - new_freq);  in clk_fs660c32_get_pe()
611 		fs->mdiv = m;  in clk_fs660c32_get_pe()
612 		fs->pe = (unsigned long)*p;  in clk_fs660c32_get_pe()
613 		fs->sdiv = si;  in clk_fs660c32_get_pe()
614 		fs->nsdiv = 1;  in clk_fs660c32_get_pe()
653 		return -1;  in clk_fs660c32_dig_get_params()
655 	/* pe fine tuning if deviation not 0: +/- 2 around computed pe value */  in clk_fs660c32_dig_get_params()
657 		fs_tmp.mdiv = fs->mdiv;  in clk_fs660c32_dig_get_params()
658 		fs_tmp.sdiv = fs->sdiv;  in clk_fs660c32_dig_get_params()
659 		fs_tmp.nsdiv = fs->nsdiv;  in clk_fs660c32_dig_get_params()
661 		if (fs->pe > 2)  in clk_fs660c32_dig_get_params()
662 			p2 = fs->pe - 2;  in clk_fs660c32_dig_get_params()
666 		for (; p2 < 32768ll && (p2 <= (fs->pe + 2)); p2++) {  in clk_fs660c32_dig_get_params()
671 			new_deviation = abs(output - new_freq);  in clk_fs660c32_dig_get_params()
675 				fs->pe = (unsigned long)p2;  in clk_fs660c32_dig_get_params()
690 	params->mdiv	= CLKGEN_READ(fs, mdiv[fs->chan]);  in quadfs_fsynt_get_hw_value_for_recalc()
691 	params->pe	= CLKGEN_READ(fs, pe[fs->chan]);  in quadfs_fsynt_get_hw_value_for_recalc()
692 	params->sdiv	= CLKGEN_READ(fs, sdiv[fs->chan]);  in quadfs_fsynt_get_hw_value_for_recalc()
694 	if (fs->data->nsdiv_present)  in quadfs_fsynt_get_hw_value_for_recalc()
695 		params->nsdiv = CLKGEN_READ(fs, nsdiv[fs->chan]);  in quadfs_fsynt_get_hw_value_for_recalc()
697 		params->nsdiv = 1;  in quadfs_fsynt_get_hw_value_for_recalc()
702 	if (!params->mdiv && !params->pe && !params->sdiv)  in quadfs_fsynt_get_hw_value_for_recalc()
705 	fs->md = params->mdiv;  in quadfs_fsynt_get_hw_value_for_recalc()
706 	fs->pe = params->pe;  in quadfs_fsynt_get_hw_value_for_recalc()
707 	fs->sdiv = params->sdiv;  in quadfs_fsynt_get_hw_value_for_recalc()
708 	fs->nsdiv = params->nsdiv;  in quadfs_fsynt_get_hw_value_for_recalc()
722 	clk_fs_get_rate = fs->data->get_rate;  in quadfs_find_best_rate()
723 	clk_fs_get_params = fs->data->get_params;  in quadfs_find_best_rate()
740 	clk_fs_get_rate = fs->data->get_rate;  in quadfs_recalc_rate()
774 	fs->md = params->mdiv;  in quadfs_program_and_enable()
775 	fs->pe = params->pe;  in quadfs_program_and_enable()
776 	fs->sdiv = params->sdiv;  in quadfs_program_and_enable()
777 	fs->nsdiv = params->nsdiv;  in quadfs_program_and_enable()
795 		return -EINVAL;  in quadfs_set_rate()
801 		return -EINVAL;  in quadfs_set_rate()
821 		struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan,  in st_clk_register_quadfs_fsynth()  argument
832 		return ERR_PTR(-EINVAL);  in st_clk_register_quadfs_fsynth()
836 		return ERR_PTR(-ENOMEM);  in st_clk_register_quadfs_fsynth()
844 	fs->data = quadfs;  in st_clk_register_quadfs_fsynth()
845 	fs->regs_base = reg;  in st_clk_register_quadfs_fsynth()
846 	fs->chan = chan;  in st_clk_register_quadfs_fsynth()
847 	fs->lock = lock;  in st_clk_register_quadfs_fsynth()
848 	fs->hw.init = &init;  in st_clk_register_quadfs_fsynth()
850 	clk = clk_register(NULL, &fs->hw);  in st_clk_register_quadfs_fsynth()
860 		struct clkgen_quadfs_data *quadfs, void __iomem *reg,  in st_of_create_quadfs_fsynths()  argument
870 	clk_data->clk_num = QUADFS_MAX_CHAN;  in st_of_create_quadfs_fsynths()
871 	clk_data->clks = kcalloc(QUADFS_MAX_CHAN, sizeof(struct clk *),  in st_of_create_quadfs_fsynths()
874 	if (!clk_data->clks) {  in st_of_create_quadfs_fsynths()
884 		if (of_property_read_string_index(np, "clock-output-names",  in st_of_create_quadfs_fsynths()
898 						    quadfs, reg, fschan,  in st_of_create_quadfs_fsynths()
906 			clk_data->clks[fschan] = clk;  in st_of_create_quadfs_fsynths()
922 	void __iomem *reg;  in st_of_quadfs_setup()  local
925 	reg = of_iomap(np, 0);  in st_of_quadfs_setup()
926 	if (!reg)  in st_of_quadfs_setup()
944 			reg, lock);  in st_of_quadfs_setup()
953 	st_of_create_quadfs_fsynths(np, pll_name, data, reg, lock);  in st_of_quadfs_setup()
963 CLK_OF_DECLARE(quadfs660C, "st,quadfs-pll", st_of_quadfs660C_setup);