Lines Matching +full:0 +full:x308
26 #define PLL_BW_GOODREF (0L)
78 .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
79 CLKGEN_FIELD(0x2f0, 0x1, 1),
80 CLKGEN_FIELD(0x2f0, 0x1, 2),
81 CLKGEN_FIELD(0x2f0, 0x1, 3) },
82 .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
83 .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
84 CLKGEN_FIELD(0x2f0, 0x1, 9),
85 CLKGEN_FIELD(0x2f0, 0x1, 10),
86 CLKGEN_FIELD(0x2f0, 0x1, 11) },
88 .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
89 CLKGEN_FIELD(0x308, 0x1, 24),
90 CLKGEN_FIELD(0x30c, 0x1, 24),
91 CLKGEN_FIELD(0x310, 0x1, 24) },
92 .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
93 CLKGEN_FIELD(0x308, 0x1f, 15),
94 CLKGEN_FIELD(0x30c, 0x1f, 15),
95 CLKGEN_FIELD(0x310, 0x1f, 15) },
96 .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
97 CLKGEN_FIELD(0x2fc, 0x1, 1),
98 CLKGEN_FIELD(0x2fc, 0x1, 2),
99 CLKGEN_FIELD(0x2fc, 0x1, 3) },
100 .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
101 .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
102 CLKGEN_FIELD(0x308, 0x7fff, 0),
103 CLKGEN_FIELD(0x30c, 0x7fff, 0),
104 CLKGEN_FIELD(0x310, 0x7fff, 0) },
105 .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
106 CLKGEN_FIELD(0x308, 0xf, 20),
107 CLKGEN_FIELD(0x30c, 0xf, 20),
108 CLKGEN_FIELD(0x310, 0xf, 20) },
110 .lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
120 .nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
121 CLKGEN_FIELD(0x2a0, 0x1, 1),
122 CLKGEN_FIELD(0x2a0, 0x1, 2),
123 CLKGEN_FIELD(0x2a0, 0x1, 3) },
124 .ndiv = CLKGEN_FIELD(0x2a4, 0x7, 16),
125 .pe = { CLKGEN_FIELD(0x2b4, 0x7fff, 0),
126 CLKGEN_FIELD(0x2b8, 0x7fff, 0),
127 CLKGEN_FIELD(0x2bc, 0x7fff, 0),
128 CLKGEN_FIELD(0x2c0, 0x7fff, 0) },
129 .sdiv = { CLKGEN_FIELD(0x2b4, 0xf, 20),
130 CLKGEN_FIELD(0x2b8, 0xf, 20),
131 CLKGEN_FIELD(0x2bc, 0xf, 20),
132 CLKGEN_FIELD(0x2c0, 0xf, 20) },
133 .npda = CLKGEN_FIELD(0x2a0, 0x1, 12),
134 .nsb = { CLKGEN_FIELD(0x2a0, 0x1, 8),
135 CLKGEN_FIELD(0x2a0, 0x1, 9),
136 CLKGEN_FIELD(0x2a0, 0x1, 10),
137 CLKGEN_FIELD(0x2a0, 0x1, 11) },
139 .nsdiv = { CLKGEN_FIELD(0x2b4, 0x1, 24),
140 CLKGEN_FIELD(0x2b8, 0x1, 24),
141 CLKGEN_FIELD(0x2bc, 0x1, 24),
142 CLKGEN_FIELD(0x2c0, 0x1, 24) },
143 .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
144 CLKGEN_FIELD(0x2b8, 0x1f, 15),
145 CLKGEN_FIELD(0x2bc, 0x1f, 15),
146 CLKGEN_FIELD(0x2c0, 0x1f, 15) },
147 .en = { CLKGEN_FIELD(0x2ac, 0x1, 0),
148 CLKGEN_FIELD(0x2ac, 0x1, 1),
149 CLKGEN_FIELD(0x2ac, 0x1, 2),
150 CLKGEN_FIELD(0x2ac, 0x1, 3) },
152 .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
193 unsigned long flags = 0, timeout = jiffies + msecs_to_jiffies(10); in quadfs_pll_enable()
228 return 0; in quadfs_pll_enable()
234 unsigned long flags = 0; in quadfs_pll_disable()
246 CLKGEN_WRITE(pll, nreset, 0); in quadfs_pll_disable()
267 return 0; in clk_fs660c32_vco_get_rate()
274 unsigned long rate = 0; in quadfs_pll_fs660c32_recalc_rate()
313 return 0; in clk_fs660c32_vco_get_params()
339 long hwrate = 0; in quadfs_pll_fs660c32_set_rate()
340 unsigned long flags = 0; in quadfs_pll_fs660c32_set_rate()
352 pr_debug("%s: %s new rate %ld [ndiv=0x%x]\n", in quadfs_pll_fs660c32_set_rate()
369 return 0; in quadfs_pll_fs660c32_set_rate()
478 CLKGEN_WRITE(fs, en[fs->chan], 0); in quadfs_fsynth_program_enable()
483 unsigned long flags = 0; in quadfs_fsynth_program_rate()
490 CLKGEN_WRITE(fs, en[fs->chan], 0); in quadfs_fsynth_program_rate()
509 unsigned long flags = 0; in quadfs_fsynth_enable()
521 CLKGEN_WRITE(fs, nrst[fs->chan], 0); in quadfs_fsynth_enable()
528 return 0; in quadfs_fsynth_enable()
534 unsigned long flags = 0; in quadfs_fsynth_disable()
552 pr_debug("%s: %s enable bit = 0x%x\n", in quadfs_fsynth_is_enabled()
572 * 0 3 in clk_fs660c32_dig_get_rate()
580 return 0; in clk_fs660c32_dig_get_rate()
617 return 0; in clk_fs660c32_get_pe()
623 int si; /* sdiv_reg (8 downto 0) */ in clk_fs660c32_dig_get_params()
627 unsigned long deviation = ~0; in clk_fs660c32_dig_get_params()
633 for (si = 0; (si <= 8) && deviation; si++) { in clk_fs660c32_dig_get_params()
636 r1 = clk_fs660c32_get_pe(0, si, &deviation, in clk_fs660c32_dig_get_params()
652 if (deviation == ~0) /* No solution found */ in clk_fs660c32_dig_get_params()
655 /* pe fine tuning if deviation not 0: +/- 2 around computed pe value */ in clk_fs660c32_dig_get_params()
664 p2 = 0; in clk_fs660c32_dig_get_params()
681 return 0; in clk_fs660c32_dig_get_params()
710 return 0; in quadfs_fsynt_get_hw_value_for_recalc()
720 unsigned long rate = 0; in quadfs_find_best_rate()
735 unsigned long rate = 0; in quadfs_recalc_rate()
743 return 0; in quadfs_recalc_rate()
762 pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n", in quadfs_round_rate()
797 memset(¶ms, 0, sizeof(struct stm_fs)); in quadfs_set_rate()
805 return 0; in quadfs_set_rate()
879 for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) { in st_of_create_quadfs_fsynths()
882 unsigned long flags = 0; in st_of_create_quadfs_fsynths()
892 if (*clk_name == '\0') in st_of_create_quadfs_fsynths()
925 reg = of_iomap(np, 0); in st_of_quadfs_setup()
929 clk_parent_name = of_clk_get_parent_name(np, 0); in st_of_quadfs_setup()