clk/socfpga/clk-pll.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
3  *  Copyright 2011-2012 Calxeda, Inc.
4  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6  * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
42 	unsigned long divf, divq, reg;  in clk_pll_recalc_rate()  local
46 	reg = readl(socfpgaclk->hw.reg);  in clk_pll_recalc_rate()
51 	divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;  in clk_pll_recalc_rate()
52 	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;  in clk_pll_recalc_rate()
63 	pll_src = readl(socfpgaclk->hw.reg);  in clk_pll_get_parent()
76 	u32 reg;  in __socfpga_pll_init()  local
79 	const char *clk_name = node->name;  in __socfpga_pll_init()
85 	of_property_read_u32(node, "reg", &reg);  in __socfpga_pll_init()
91 	clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");  in __socfpga_pll_init()
95 	pll_clk->hw.reg = clk_mgr_base_addr + reg;  in __socfpga_pll_init()
97 	of_property_read_string(node, "clock-output-names", &clk_name);  in __socfpga_pll_init()
105 	pll_clk->hw.hw.init = &init;  in __socfpga_pll_init()
107 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;  in __socfpga_pll_init()
109 	clk = clk_register(NULL, &pll_clk->hw.hw);  in __socfpga_pll_init()