clk/socfpga/clk-agilex.c

1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/agilex-clock.h>
13 #include "stratix10-clk.h"
18 	{ .fw_name = "cb-intosc-hs-div2-clk",
19 	  .name = "cb-intosc-hs-div2-clk", },
20 	{ .fw_name = "f2s-free-clk",
21 	  .name = "f2s-free-clk", },
27 	{ .fw_name = "cb-intosc-hs-div2-clk",
28 	  .name = "cb-intosc-hs-div2-clk", },
38 	{ .fw_name = "cb-intosc-hs-div2-clk",
39 	  .name = "cb-intosc-hs-div2-clk", },
40 	{ .fw_name = "f2s-free-clk",
41 	  .name = "f2s-free-clk", },
51 	{ .fw_name = "cb-intosc-hs-div2-clk",
52 	  .name = "cb-intosc-hs-div2-clk", },
53 	{ .fw_name = "f2s-free-clk",
54 	  .name = "f2s-free-clk", },
64 	{ .fw_name = "cb-intosc-hs-div2-clk",
65 	  .name = "cb-intosc-hs-div2-clk", },
66 	{ .fw_name = "f2s-free-clk",
67 	  .name = "f2s-free-clk", },
77 	{ .fw_name = "cb-intosc-hs-div2-clk",
78 	  .name = "cb-intosc-hs-div2-clk", },
79 	{ .fw_name = "f2s-free-clk",
80 	  .name = "f2s-free-clk", },
90 	{ .fw_name = "cb-intosc-hs-div2-clk",
91 	  .name = "cb-intosc-hs-div2-clk", },
92 	{ .fw_name = "f2s-free-clk",
93 	  .name = "f2s-free-clk", },
103 	{ .fw_name = "cb-intosc-hs-div2-clk",
104 	  .name = "cb-intosc-hs-div2-clk", },
105 	{ .fw_name = "f2s-free-clk",
106 	  .name = "f2s-free-clk", },
116 	{ .fw_name = "cb-intosc-hs-div2-clk",
117 	  .name = "cb-intosc-hs-div2-clk", },
118 	{ .fw_name = "f2s-free-clk",
119 	  .name = "f2s-free-clk", },
129 	{ .fw_name = "cb-intosc-hs-div2-clk",
130 	  .name = "cb-intosc-hs-div2-clk", },
131 	{ .fw_name = "f2s-free-clk",
132 	  .name = "f2s-free-clk", },
142 	{ .fw_name = "cb-intosc-hs-div2-clk",
143 	  .name = "cb-intosc-hs-div2-clk", },
144 	{ .fw_name = "f2s-free-clk",
145 	  .name = "f2s-free-clk", },
155 	{ .fw_name = "cb-intosc-hs-div2-clk",
156 	  .name = "cb-intosc-hs-div2-clk", },
157 	{ .fw_name = "f2s-free-clk",
158 	  .name = "f2s-free-clk", },
169 	{ .fw_name = "f2s-free-clk",
170 	  .name = "f2s-free-clk", },
296 	void __iomem *base = data->base;  in agilex_clk_register_c_perip()
306 		data->clk_data.clks[clks[i].id] = clk;  in agilex_clk_register_c_perip()
315 	void __iomem *base = data->base;  in agilex_clk_register_cnt_perip()
325 		data->clk_data.clks[clks[i].id] = clk;  in agilex_clk_register_cnt_perip()
334 	void __iomem *base = data->base;  in agilex_clk_register_gate()
344 		data->clk_data.clks[clks[i].id] = clk;  in agilex_clk_register_gate()
354 	void __iomem *base = data->base;  in agilex_clk_register_pll()
364 		data->clk_data.clks[clks[i].id] = clk;  in agilex_clk_register_pll()
373 	struct device_node *np = pdev->dev.of_node;  in __socfpga_agilex_clk_init()
374 	struct device *dev = &pdev->dev;  in __socfpga_agilex_clk_init()
388 		return ERR_PTR(-ENOMEM);  in __socfpga_agilex_clk_init()
390 	clk_data->base = base;  in __socfpga_agilex_clk_init()
393 		return ERR_PTR(-ENOMEM);  in __socfpga_agilex_clk_init()
395 	clk_data->clk_data.clks = clk_table;  in __socfpga_agilex_clk_init()
396 	clk_data->clk_data.clk_num = nr_clks;  in __socfpga_agilex_clk_init()
397 	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);  in __socfpga_agilex_clk_init()
427 	{ .compatible = "intel,agilex-clkmgr",
435 		.name	= "agilex-clkmgr",