Lines Matching +full:clk +full:- +full:source
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
37 uint32_t source : 8; /* source index + 1 (0 == none) */ member
46 /* For fixed-factor ones */
66 .source = 1 + R9A06G032_##_src, .name = _n, \
70 .source = 1 + R9A06G032_##_src, .name = _n, \
77 .source = 1 + R9A06G032_##_src, .name = _n, \
81 .source = 1 + R9A06G032_##_src, .name = _n, \
86 .source = 1 + R9A06G032_##_src, .name = _n, \
288 .source = 1 + R9A06G032_DIV_UART,
297 .source = 1 + R9A06G032_DIV_P2_PG,
323 u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); in clk_rdesc_set()
334 u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); in clk_rdesc_get()
358 struct clk *clk; in create_add_module_clock() local
361 clk = of_clk_get_from_provider(clkspec); in create_add_module_clock()
362 if (IS_ERR(clk)) in create_add_module_clock()
363 return PTR_ERR(clk); in create_add_module_clock()
367 clk_put(clk); in create_add_module_clock()
371 error = pm_clk_add_clk(dev, clk); in create_add_module_clock()
374 clk_put(clk); in create_add_module_clock()
383 struct device_node *np = dev->of_node; in r9a06g032_attach_dev()
389 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, in r9a06g032_attach_dev()
391 if (clkspec.np != pd->dev.of_node) in r9a06g032_attach_dev()
416 struct device_node *np = dev->of_node; in r9a06g032_add_clk_domain()
421 return -ENOMEM; in r9a06g032_add_clk_domain()
423 pd->name = np->name; in r9a06g032_add_clk_domain()
424 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | in r9a06g032_add_clk_domain()
426 pd->attach_dev = r9a06g032_attach_dev; in r9a06g032_add_clk_domain()
427 pd->detach_dev = r9a06g032_detach_dev; in r9a06g032_add_clk_domain()
440 WARN_ON(!g->gate); in r9a06g032_clk_gate_set()
442 spin_lock_irqsave(&clocks->lock, flags); in r9a06g032_clk_gate_set()
443 clk_rdesc_set(clocks, g->gate, on); in r9a06g032_clk_gate_set()
444 /* De-assert reset */ in r9a06g032_clk_gate_set()
445 if (g->reset) in r9a06g032_clk_gate_set()
446 clk_rdesc_set(clocks, g->reset, 1); in r9a06g032_clk_gate_set()
447 spin_unlock_irqrestore(&clocks->lock, flags); in r9a06g032_clk_gate_set()
456 if (g->ready || g->midle) { in r9a06g032_clk_gate_set()
457 spin_lock_irqsave(&clocks->lock, flags); in r9a06g032_clk_gate_set()
458 if (g->ready) in r9a06g032_clk_gate_set()
459 clk_rdesc_set(clocks, g->ready, on); in r9a06g032_clk_gate_set()
461 if (g->midle) in r9a06g032_clk_gate_set()
462 clk_rdesc_set(clocks, g->midle, !on); in r9a06g032_clk_gate_set()
463 spin_unlock_irqrestore(&clocks->lock, flags); in r9a06g032_clk_gate_set()
472 r9a06g032_clk_gate_set(g->clocks, &g->gate, 1); in r9a06g032_clk_gate_enable()
480 r9a06g032_clk_gate_set(g->clocks, &g->gate, 0); in r9a06g032_clk_gate_disable()
488 if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset)) in r9a06g032_clk_gate_is_enabled()
491 return clk_rdesc_get(g->clocks, g->gate.gate); in r9a06g032_clk_gate_is_enabled()
500 static struct clk *
505 struct clk *clk; in r9a06g032_register_gate() local
513 init.name = desc->name; in r9a06g032_register_gate()
519 g->clocks = clocks; in r9a06g032_register_gate()
520 g->index = desc->index; in r9a06g032_register_gate()
521 g->gate = desc->gate; in r9a06g032_register_gate()
522 g->hw.init = &init; in r9a06g032_register_gate()
529 if (r9a06g032_clk_gate_is_enabled(&g->hw)) { in r9a06g032_register_gate()
531 pr_debug("%s was enabled, making read-only\n", desc->name); in r9a06g032_register_gate()
534 clk = clk_register(NULL, &g->hw); in r9a06g032_register_gate()
535 if (IS_ERR(clk)) { in r9a06g032_register_gate()
539 return clk; in r9a06g032_register_gate()
559 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); in r9a06g032_div_recalc_rate() local
560 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); in r9a06g032_div_recalc_rate()
563 if (div < clk->min) in r9a06g032_div_recalc_rate()
564 div = clk->min; in r9a06g032_div_recalc_rate()
565 else if (div > clk->max) in r9a06g032_div_recalc_rate()
566 div = clk->max; in r9a06g032_div_recalc_rate()
577 r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk, in r9a06g032_div_clamp_div() argument
584 if (div <= clk->min) in r9a06g032_div_clamp_div()
585 return clk->min; in r9a06g032_div_clamp_div()
586 if (div >= clk->max) in r9a06g032_div_clamp_div()
587 return clk->max; in r9a06g032_div_clamp_div()
589 for (i = 0; clk->table_size && i < clk->table_size - 1; i++) { in r9a06g032_div_clamp_div()
590 if (div >= clk->table[i] && div <= clk->table[i + 1]) { in r9a06g032_div_clamp_div()
591 unsigned long m = rate - in r9a06g032_div_clamp_div()
592 DIV_ROUND_UP(prate, clk->table[i]); in r9a06g032_div_clamp_div()
594 DIV_ROUND_UP(prate, clk->table[i + 1]) - in r9a06g032_div_clamp_div()
600 div = p >= m ? clk->table[i] : clk->table[i + 1]; in r9a06g032_div_clamp_div()
611 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); in r9a06g032_div_round_rate() local
615 hw->clk, rate, *prate, div); in r9a06g032_div_round_rate()
617 clk->min, DIV_ROUND_UP(*prate, clk->min), in r9a06g032_div_round_rate()
618 clk->max, DIV_ROUND_UP(*prate, clk->max)); in r9a06g032_div_round_rate()
620 div = r9a06g032_div_clamp_div(clk, rate, *prate); in r9a06g032_div_round_rate()
623 * that is 16 times the baud rate -- and that is wildly outside the in r9a06g032_div_round_rate()
630 if (clk->index == R9A06G032_DIV_UART || in r9a06g032_div_round_rate()
631 clk->index == R9A06G032_DIV_P2_PG) { in r9a06g032_div_round_rate()
633 return clk_get_rate(hw->clk); in r9a06g032_div_round_rate()
635 pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk, in r9a06g032_div_round_rate()
644 struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw); in r9a06g032_div_set_rate() local
647 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); in r9a06g032_div_set_rate()
649 pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk, in r9a06g032_div_set_rate()
670 static struct clk *
676 struct clk *clk; in r9a06g032_register_div() local
684 init.name = desc->name; in r9a06g032_register_div()
690 div->clocks = clocks; in r9a06g032_register_div()
691 div->index = desc->index; in r9a06g032_register_div()
692 div->reg = desc->reg; in r9a06g032_register_div()
693 div->hw.init = &init; in r9a06g032_register_div()
694 div->min = desc->div_min; in r9a06g032_register_div()
695 div->max = desc->div_max; in r9a06g032_register_div()
697 for (i = 0; i < ARRAY_SIZE(div->table) && in r9a06g032_register_div()
698 i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) { in r9a06g032_register_div()
699 div->table[div->table_size++] = desc->div_table[i]; in r9a06g032_register_div()
702 clk = clk_register(NULL, &div->hw); in r9a06g032_register_div()
703 if (IS_ERR(clk)) { in r9a06g032_register_div()
707 return clk; in r9a06g032_register_div()
712 * peripherals that have two potential clock source and two gates, one for
713 * each of the clock source - the used clock source (for all sub clocks)
715 * That single bit affects all sub-clocks, and therefore needs to change the
736 return clk_rdesc_get(set->clocks, set->selector); in r9a06g032_clk_mux_get_parent()
744 clk_rdesc_set(set->clocks, set->selector, !!index); in r9a06g032_clk_mux_set_parent()
754 static struct clk *
759 struct clk *clk; in r9a06g032_register_bitsel() local
772 init.name = desc->name; in r9a06g032_register_bitsel()
778 g->clocks = clocks; in r9a06g032_register_bitsel()
779 g->index = desc->index; in r9a06g032_register_bitsel()
780 g->selector = desc->dual.sel; in r9a06g032_register_bitsel()
781 g->hw.init = &init; in r9a06g032_register_bitsel()
783 clk = clk_register(NULL, &g->hw); in r9a06g032_register_bitsel()
784 if (IS_ERR(clk)) { in r9a06g032_register_bitsel()
788 return clk; in r9a06g032_register_bitsel()
805 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector); in r9a06g032_clk_dualgate_setenable()
808 r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0); in r9a06g032_clk_dualgate_setenable()
809 r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable); in r9a06g032_clk_dualgate_setenable()
833 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector); in r9a06g032_clk_dualgate_is_enabled()
835 return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate); in r9a06g032_clk_dualgate_is_enabled()
844 static struct clk *
851 struct clk *clk; in r9a06g032_register_dualgate() local
858 g->clocks = clocks; in r9a06g032_register_dualgate()
859 g->index = desc->index; in r9a06g032_register_dualgate()
860 g->selector = sel; in r9a06g032_register_dualgate()
861 g->gate[0].gate = desc->dual.g1; in r9a06g032_register_dualgate()
862 g->gate[0].reset = desc->dual.r1; in r9a06g032_register_dualgate()
863 g->gate[1].gate = desc->dual.g2; in r9a06g032_register_dualgate()
864 g->gate[1].reset = desc->dual.r2; in r9a06g032_register_dualgate()
866 init.name = desc->name; in r9a06g032_register_dualgate()
871 g->hw.init = &init; in r9a06g032_register_dualgate()
877 if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) { in r9a06g032_register_dualgate()
879 pr_debug("%s was enabled, making read-only\n", desc->name); in r9a06g032_register_dualgate()
882 clk = clk_register(NULL, &g->hw); in r9a06g032_register_dualgate()
883 if (IS_ERR(clk)) { in r9a06g032_register_dualgate()
887 return clk; in r9a06g032_register_dualgate()
897 struct device *dev = &pdev->dev; in r9a06g032_clocks_probe()
898 struct device_node *np = dev->of_node; in r9a06g032_clocks_probe()
900 struct clk **clks; in r9a06g032_clocks_probe()
901 struct clk *mclk; in r9a06g032_clocks_probe()
907 clks = devm_kcalloc(dev, R9A06G032_CLOCK_COUNT, sizeof(struct clk *), in r9a06g032_clocks_probe()
910 return -ENOMEM; in r9a06g032_clocks_probe()
912 spin_lock_init(&clocks->lock); in r9a06g032_clocks_probe()
914 clocks->data.clks = clks; in r9a06g032_clocks_probe()
915 clocks->data.clk_num = R9A06G032_CLOCK_COUNT; in r9a06g032_clocks_probe()
921 clocks->reg = of_iomap(np, 0); in r9a06g032_clocks_probe()
922 if (WARN_ON(!clocks->reg)) in r9a06g032_clocks_probe()
923 return -ENOMEM; in r9a06g032_clocks_probe()
926 const char *parent_name = d->source ? in r9a06g032_clocks_probe()
927 __clk_get_name(clocks->data.clks[d->source - 1]) : in r9a06g032_clocks_probe()
929 struct clk *clk = NULL; in r9a06g032_clocks_probe() local
931 switch (d->type) { in r9a06g032_clocks_probe()
933 clk = clk_register_fixed_factor(NULL, d->name, in r9a06g032_clocks_probe()
935 d->mul, d->div); in r9a06g032_clocks_probe()
938 clk = r9a06g032_register_gate(clocks, parent_name, d); in r9a06g032_clocks_probe()
941 clk = r9a06g032_register_div(clocks, parent_name, d); in r9a06g032_clocks_probe()
945 uart_group_sel[d->dual.group] = d->dual.sel; in r9a06g032_clocks_probe()
946 clk = r9a06g032_register_bitsel(clocks, parent_name, d); in r9a06g032_clocks_probe()
949 clk = r9a06g032_register_dualgate(clocks, parent_name, in r9a06g032_clocks_probe()
951 uart_group_sel[d->dual.group]); in r9a06g032_clocks_probe()
954 clocks->data.clks[d->index] = clk; in r9a06g032_clocks_probe()
956 error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data); in r9a06g032_clocks_probe()
969 { .compatible = "renesas,r9a06g032-sysctrl" },
975 .name = "renesas,r9a06g032-sysctrl",