clk/renesas/r8a779a0-cpg-mssr.c

96 	DEF_PLL(".pll20", CLK_PLL20,	0x0834),
97 	DEF_PLL(".pll21", CLK_PLL21,	0x0838),
98 	DEF_PLL(".pll30", CLK_PLL30,	0x083c),
99 	DEF_PLL(".pll31", CLK_PLL31,	0x0840),
135 	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),
136 	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),
137 	DEF_DIV6P1("csi0",	R8A779A0_CLK_CSI0,	CLK_PLL5_DIV4,	0x880),
166 	parent = clks[core->parent & 0xffff];	/* some types use high bits */  in rcar_r8a779a0_cpg_clk_register()
182 		mult = (((value >> 24) & 0x7f) + 1) * 2;  in rcar_r8a779a0_cpg_clk_register()
196 			div = core->div & 0xffff;  in rcar_r8a779a0_cpg_clk_register()
218 					 __clk_get_name(parent), 0, mult, div);  in rcar_r8a779a0_cpg_clk_register()
228  * 0  0	 16.66 x 1	x128	x216	x128	x144	x192	/16
229  * 0  1	 20    x 1	x106	x180	x106	x120	x160	/19
230  * 1  0	 Prohibited setting
231  * 1  1	 33.33 / 2	x128	x216	x128	x144	x192	/32
240 	{ 0,		0,	0,	0,	0,	0,	},
256 	return 0;  in r8a779a0_cpg_mssr_init()