clk/renesas/clk-rz.c

1 // SPDX-License-Identifier: GPL-2.0
6  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 #include <linux/clk-provider.h>
20 	void __iomem *reg;  member
31 /* -----------------------------------------------------------------------------
67 	/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */  in rz_cpg_register_clock()
68 	if (!cpg->reg)  in rz_cpg_register_clock()
69 		return ERR_PTR(-ENXIO);  in rz_cpg_register_clock()
71 	/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)  in rz_cpg_register_clock()
76 		val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;  in rz_cpg_register_clock()
78 		val = readl(cpg->reg + CPG_FRQCR2) & 3;  in rz_cpg_register_clock()
80 		return ERR_PTR(-EINVAL);  in rz_cpg_register_clock()
93 	num_clks = of_property_count_strings(np, "clock-output-names");  in rz_cpg_clocks_init()
101 	cpg->data.clks = clks;  in rz_cpg_clocks_init()
102 	cpg->data.clk_num = num_clks;  in rz_cpg_clocks_init()
104 	cpg->reg = of_iomap(np, 0);  in rz_cpg_clocks_init()
110 		of_property_read_string_index(np, "clock-output-names", i, &name);  in rz_cpg_clocks_init()
117 			cpg->data.clks[i] = clk;  in rz_cpg_clocks_init()
120 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);  in rz_cpg_clocks_init()
124 CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);