1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27  * struct div6_clock - CPG 6 bit divider clock
28  * @hw: handle between common and hardware-specific interfaces
29  * @reg: IO-remapped register
30  * @div: divisor value (1-64)
38 	void __iomem *reg;  member
53 	val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))  in cpg_div6_clock_enable()
54 	    | CPG_DIV6_DIV(clock->div - 1);  in cpg_div6_clock_enable()
55 	writel(val, clock->reg);  in cpg_div6_clock_enable()
65 	val = readl(clock->reg);  in cpg_div6_clock_disable()
68 	 * DIV6 clocks require the divisor field to be non-zero when stopping  in cpg_div6_clock_disable()
70 	 * re-enabled later if the divisor field is changed when stopping the  in cpg_div6_clock_disable()
75 	writel(val, clock->reg);  in cpg_div6_clock_disable()
82 	return !(readl(clock->reg) & CPG_DIV6_CKSTP);  in cpg_div6_clock_is_enabled()
90 	return parent_rate / clock->div;  in cpg_div6_clock_recalc_rate()
120 	clock->div = div;  in cpg_div6_clock_set_rate()
122 	val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;  in cpg_div6_clock_set_rate()
125 		writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);  in cpg_div6_clock_set_rate()
136 	if (clock->src_width == 0)  in cpg_div6_clock_get_parent()
139 	hw_index = (readl(clock->reg) >> clock->src_shift) &  in cpg_div6_clock_get_parent()
140 		   (BIT(clock->src_width) - 1);  in cpg_div6_clock_get_parent()
142 		if (clock->parents[i] == hw_index)  in cpg_div6_clock_get_parent()
158 		return -EINVAL;  in cpg_div6_clock_set_parent()
160 	mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);  in cpg_div6_clock_set_parent()
161 	hw_index = clock->parents[index];  in cpg_div6_clock_set_parent()
163 	writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),  in cpg_div6_clock_set_parent()
164 	       clock->reg);  in cpg_div6_clock_set_parent()
191 		 * R/SH-Mobile SoCs, while the resume functionality is only  in cpg_div6_clock_notifier_call()
192 		 * needed on R-Car Gen3.  in cpg_div6_clock_notifier_call()
194 		if (__clk_get_enable_count(clock->hw.clk))  in cpg_div6_clock_notifier_call()
195 			cpg_div6_clock_enable(&clock->hw);  in cpg_div6_clock_notifier_call()
197 			cpg_div6_clock_disable(&clock->hw);  in cpg_div6_clock_notifier_call()
205  * cpg_div6_register - Register a DIV6 clock
208  * @parent_names: Array containing the names of the parent clocks
209  * @reg: Mapped register used to control the DIV6 clock
215 				      void __iomem *reg,  in cpg_div6_register()  argument
226 		return ERR_PTR(-ENOMEM);  in cpg_div6_register()
228 	clock->reg = reg;  in cpg_div6_register()
234 	clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;  in cpg_div6_register()
239 		clock->src_shift = clock->src_width = 0;  in cpg_div6_register()
242 		/* clock with EXSRC bits 6-7 */  in cpg_div6_register()
243 		clock->src_shift = 6;  in cpg_div6_register()
244 		clock->src_width = 2;  in cpg_div6_register()
247 		/* VCLK with EXSRC bits 12-14 */  in cpg_div6_register()
248 		clock->src_shift = 12;  in cpg_div6_register()
249 		clock->src_width = 3;  in cpg_div6_register()
254 		clk = ERR_PTR(-EINVAL);  in cpg_div6_register()
262 			clock->parents[valid_parents] = i;  in cpg_div6_register()
274 	clock->hw.init = &init;  in cpg_div6_register()
276 	clk = clk_register(NULL, &clock->hw);  in cpg_div6_register()
281 		clock->nb.notifier_call = cpg_div6_clock_notifier_call;  in cpg_div6_register()
282 		raw_notifier_chain_register(notifiers, &clock->nb);  in cpg_div6_register()
296 	const char *clk_name = np->name;  in cpg_div6_clock_init()
297 	void __iomem *reg;  in cpg_div6_clock_init()  local
313 	reg = of_iomap(np, 0);  in cpg_div6_clock_init()
314 	if (reg == NULL) {  in cpg_div6_clock_init()
321 	of_property_read_string(np, "clock-output-names", &clk_name);  in cpg_div6_clock_init()
326 	clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL);  in cpg_div6_clock_init()
339 	if (reg)  in cpg_div6_clock_init()
340 		iounmap(reg);  in cpg_div6_clock_init()
343 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);