Lines Matching +full:0 +full:x48
27 .l_reg = 0x4,
28 .m_reg = 0x8,
29 .n_reg = 0xc,
30 .config_reg = 0x14,
31 .mode_reg = 0x0,
32 .status_reg = 0x18,
48 { P_PXO, 0 },
69 { 27000000, P_PXO, 1, 0, 0 },
85 { 27000000, P_PXO, 1, 0, 0 },
90 .ns_reg = 0x48,
91 .md_reg = 0x4c,
105 .src_sel_shift = 0,
110 .enable_reg = 0x48,
127 .halt_reg = 0x50,
131 .enable_reg = 0x48,
144 .reg = 0x48,
148 .enable_reg = 0x48,
160 .halt_reg = 0x50,
161 .halt_bit = 0,
164 .enable_reg = 0x48,
177 .reg = 0x48,
211 .src_sel_shift = 0, \
265 .halt_bit = 0, \
300 CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
301 CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
302 CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
303 CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
318 { 27000000, P_PXO, 1, 0, 0 },
335 { 27000000, P_PXO, 1, 0, 0 },
340 .ns_reg = 0x54,
341 .md_reg = 0x58,
355 .src_sel_shift = 0,
360 .enable_reg = 0x54,
373 .halt_reg = 0x5c,
374 .halt_bit = 0,
377 .enable_reg = 0x54,
390 .reg = 0x54,
408 .ns_reg = 0xcc,
409 .md_reg = 0xd0,
423 .src_sel_shift = 0,
428 .enable_reg = 0xcc,
445 .halt_reg = 0xd4,
446 .halt_bit = 0,
449 .enable_reg = 0xcc,
462 .halt_reg = 0xd4,
466 .enable_reg = 0xcc,
517 .max_register = 0xfc,
544 regmap_read(regmap, 0x4, &val); in lcc_msm8960_probe()
545 if (val == 0x12) { in lcc_msm8960_probe()
555 regmap_write(regmap, 0xc4, 0x1); in lcc_msm8960_probe()