Lines Matching +full:0 +full:x1004
20 #define CX_GMU_CBCR_SLEEP_MASK 0xF
22 #define CX_GMU_CBCR_WAKE_MASK 0xF
25 #define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT)
38 { 249600000, 2000000000, 0 },
42 .offset = 0x100,
59 { P_BI_TCXO, 0 },
73 F(19200000, P_BI_TCXO, 1, 0, 0),
74 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
79 .cmd_rcgr = 0x1120,
80 .mnd_width = 0,
94 .halt_reg = 0x107c,
97 .enable_reg = 0x107c,
98 .enable_mask = BIT(0),
107 .halt_reg = 0x1098,
110 .enable_reg = 0x1098,
111 .enable_mask = BIT(0),
125 .halt_reg = 0x108c,
128 .enable_reg = 0x108c,
129 .enable_mask = BIT(0),
138 .halt_reg = 0x1004,
141 .enable_reg = 0x1004,
142 .enable_mask = BIT(0),
151 .halt_reg = 0x109c,
154 .enable_reg = 0x109c,
155 .enable_mask = BIT(0),
164 .gdscr = 0x106c,
165 .gds_hw_ctrl = 0x1540,
174 .gdscr = 0x100c,
175 .clamp_io_ctrl = 0x1508,
203 .max_register = 0x8008,
232 gpu_cc_pll_config.l = 0x12; in gpu_cc_sc7180_probe()
233 gpu_cc_pll_config.alpha = 0xc000; in gpu_cc_sc7180_probe()
234 gpu_cc_pll_config.config_ctl_val = 0x20485699; in gpu_cc_sc7180_probe()
235 gpu_cc_pll_config.config_ctl_hi_val = 0x00002067; in gpu_cc_sc7180_probe()
236 gpu_cc_pll_config.user_ctl_val = 0x00000001; in gpu_cc_sc7180_probe()
237 gpu_cc_pll_config.user_ctl_hi_val = 0x00004805; in gpu_cc_sc7180_probe()
238 gpu_cc_pll_config.test_ctl_hi_val = 0x40000000; in gpu_cc_sc7180_probe()
245 value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT; in gpu_cc_sc7180_probe()
246 regmap_update_bits(regmap, 0x1098, mask, value); in gpu_cc_sc7180_probe()
249 regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK, in gpu_cc_sc7180_probe()