Lines Matching +full:xo +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
22 #include "clk-regmap.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
26 #include "clk-regmap-divider.h"
46 * struct clk_fepll_vco - vco feedback divider corresponds for FEPLL clocks
62 * struct clk_fepll - clk divider corresponds to FEPLL clocks
82 { P_FEPLL200, 1 },
87 "xo",
94 { P_FEPLL200, 1 },
98 "xo",
108 "xo",
114 { P_DDRPLL, 1 },
119 "xo",
126 { P_FEPLLWCSS2G, 1 },
130 "xo",
136 { P_FEPLLWCSS5G, 1 },
140 "xo",
146 { P_FEPLL125DLY, 1 },
150 "xo",
158 { P_DDRPLLAPSS, 1 },
168 "xo",
175 F(48000000, P_XO, 1, 0, 0),
176 F(200000000, P_FEPLL200, 1, 0, 0),
205 .num_parents = 1,
222 .num_parents = 1,
229 F(19050000, P_FEPLL200, 10.5, 1, 1),
256 .num_parents = 1,
286 .num_parents = 1,
294 F(960000, P_XO, 12, 1, 4),
295 F(4800000, P_XO, 1, 1, 10),
296 F(9600000, P_XO, 1, 1, 5),
297 F(15000000, P_XO, 1, 1, 3),
298 F(19200000, P_XO, 1, 2, 5),
299 F(24000000, P_XO, 1, 1, 2),
300 F(48000000, P_XO, 1, 0, 0),
328 .num_parents = 1,
359 .num_parents = 1,
367 F(1843200, P_FEPLL200, 1, 144, 15625),
368 F(3686400, P_FEPLL200, 1, 288, 15625),
369 F(7372800, P_FEPLL200, 1, 576, 15625),
370 F(14745600, P_FEPLL200, 1, 1152, 15625),
371 F(16000000, P_FEPLL200, 1, 2, 25),
372 F(24000000, P_XO, 1, 1, 2),
373 F(32000000, P_FEPLL200, 1, 4, 25),
374 F(40000000, P_FEPLL200, 1, 1, 5),
375 F(46400000, P_FEPLL200, 1, 29, 125),
376 F(48000000, P_XO, 1, 0, 0),
405 .num_parents = 1,
435 .num_parents = 1,
443 F(1250000, P_FEPLL200, 1, 16, 0),
444 F(2500000, P_FEPLL200, 1, 8, 0),
445 F(5000000, P_FEPLL200, 1, 4, 0),
473 .num_parents = 1,
504 .num_parents = 1,
535 .num_parents = 1,
543 F(144000, P_XO, 1, 3, 240),
544 F(400000, P_XO, 1, 1, 0),
545 F(20000000, P_FEPLL500, 1, 1, 25),
546 F(25000000, P_FEPLL500, 1, 1, 20),
547 F(50000000, P_FEPLL500, 1, 1, 10),
548 F(100000000, P_FEPLL500, 1, 1, 5),
549 F(192000000, P_DDRPLL, 1, 0, 0),
568 F(48000000, P_XO, 1, 0, 0),
569 F(200000000, P_FEPLL200, 1, 0, 0),
570 F(384000000, P_DDRPLLAPSS, 1, 0, 0),
571 F(413000000, P_DDRPLLAPSS, 1, 0, 0),
572 F(448000000, P_DDRPLLAPSS, 1, 0, 0),
573 F(488000000, P_DDRPLLAPSS, 1, 0, 0),
574 F(500000000, P_FEPLL500, 1, 0, 0),
575 F(512000000, P_DDRPLLAPSS, 1, 0, 0),
576 F(537000000, P_DDRPLLAPSS, 1, 0, 0),
577 F(565000000, P_DDRPLLAPSS, 1, 0, 0),
578 F(597000000, P_DDRPLLAPSS, 1, 0, 0),
579 F(632000000, P_DDRPLLAPSS, 1, 0, 0),
580 F(672000000, P_DDRPLLAPSS, 1, 0, 0),
581 F(716000000, P_DDRPLLAPSS, 1, 0, 0),
600 F(48000000, P_XO, 1, 0, 0),
629 .num_parents = 1,
647 .num_parents = 1,
661 "xo",
663 .num_parents = 1,
679 .num_parents = 1,
697 .num_parents = 1,
708 .enable_mask = BIT(1),
714 .num_parents = 1,
731 .num_parents = 1,
747 .num_parents = 1,
765 .num_parents = 1,
781 .num_parents = 1,
797 .num_parents = 1,
813 .num_parents = 1,
829 .num_parents = 1,
846 .num_parents = 1,
862 .num_parents = 1,
878 .num_parents = 1,
894 .num_parents = 1,
910 .num_parents = 1,
928 .num_parents = 1,
944 .num_parents = 1,
960 .num_parents = 1,
976 .num_parents = 1,
1011 .num_parents = 1,
1027 .num_parents = 1,
1043 .num_parents = 1,
1051 F(125000000, P_FEPLL125DLY, 1, 0, 0),
1070 F(48000000, P_XO, 1, 0, 0),
1071 F(250000000, P_FEPLLWCSS2G, 1, 0, 0),
1099 .num_parents = 1,
1114 "xo",
1116 .num_parents = 1,
1133 .num_parents = 1,
1140 F(48000000, P_XO, 1, 0, 0),
1141 F(250000000, P_FEPLLWCSS5G, 1, 0, 0),
1168 .num_parents = 1,
1183 "xo",
1185 .num_parents = 1,
1202 .num_parents = 1,
1213 const struct clk_fepll_vco *pll_vco = pll_div->pll_vco; in clk_fepll_vco_calc_rate()
1217 regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv); in clk_fepll_vco_calc_rate()
1218 refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) & in clk_fepll_vco_calc_rate()
1219 (BIT(pll_vco->refclkdiv_width) - 1); in clk_fepll_vco_calc_rate()
1220 fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) & in clk_fepll_vco_calc_rate()
1221 (BIT(pll_vco->fdbkdiv_width) - 1); in clk_fepll_vco_calc_rate()
1258 f = qcom_find_freq(pll->freq_tbl, rate); in clk_cpu_div_round_rate()
1260 return -EINVAL; in clk_cpu_div_round_rate()
1262 p_hw = clk_hw_get_parent_by_index(hw, f->src); in clk_cpu_div_round_rate()
1265 return f->freq; in clk_cpu_div_round_rate()
1281 f = qcom_find_freq(pll->freq_tbl, rate); in clk_cpu_div_set_rate()
1283 return -EINVAL; in clk_cpu_div_set_rate()
1285 mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift; in clk_cpu_div_set_rate()
1286 ret = regmap_update_bits(pll->cdiv.clkr.regmap, in clk_cpu_div_set_rate()
1287 pll->cdiv.reg, mask, in clk_cpu_div_set_rate()
1288 f->pre_div << pll->cdiv.shift); in clk_cpu_div_set_rate()
1293 udelay(1); in clk_cpu_div_set_rate()
1312 regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); in clk_cpu_div_recalc_rate()
1313 cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); in clk_cpu_div_recalc_rate()
1321 pre_div = (cdiv + 1) * 2; in clk_cpu_div_recalc_rate()
1365 "xo",
1367 .num_parents = 1,
1385 u32 cdiv, pre_div = 1; in clk_regmap_clk_div_recalc_rate()
1389 if (pll->fixed_div) { in clk_regmap_clk_div_recalc_rate()
1390 pre_div = pll->fixed_div; in clk_regmap_clk_div_recalc_rate()
1392 regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); in clk_regmap_clk_div_recalc_rate()
1393 cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); in clk_regmap_clk_div_recalc_rate()
1395 for (clkt = pll->div_table; clkt->div; clkt++) { in clk_regmap_clk_div_recalc_rate()
1396 if (clkt->val == cdiv) in clk_regmap_clk_div_recalc_rate()
1397 pre_div = clkt->div; in clk_regmap_clk_div_recalc_rate()
1417 "xo",
1419 .num_parents = 1,
1432 "xo",
1434 .num_parents = 1,
1447 "xo",
1449 .num_parents = 1,
1462 "xo",
1464 .num_parents = 1,
1477 "xo",
1479 .num_parents = 1,
1488 { 1, 16 },
1502 "xo",
1504 .num_parents = 1,
1520 "xo",
1522 .num_parents = 1,
1531 F(48000000, P_XO, 1, 0, 0),
1559 .num_parents = 1,
1644 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
1650 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
1667 [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
1730 { .compatible = "qcom,gcc-ipq4019" },
1774 .name = "qcom,gcc-ipq4019",
1791 MODULE_ALIAS("platform:gcc-ipq4019");