clk/qcom/clk-cpu-8996.c

1 // SPDX-License-Identifier: GPL-2.0
7  * Each of the CPU clusters (Power and Perf) on msm8996 are
12  *                              +-------+
14  *           +------------------>0      |
16  *                    PLL/2     | SMUX  +----+
17  *                      +------->1      |    |
19  *                      |       +-------+    |    +-------+
20  *                      |                    +---->0      |
22  * +---------------+    |             +----------->1      | CPU clk
23  * |Primary PLL    +----+ PLL_EARLY   |           |       +------>
24  * |               +------+-----------+    +------>2 PMUX |
25  * +---------------+      |                |      |       |
26  *                        |   +------+     |   +-->3      |
27  *                        +--^+  ACD +-----+   |  +-------+
28  * +---------------+          +------+         |
30  * |               +---------------------------+
31  * +---------------+         PLL_EARLY
44  *  Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
46  *  Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
53 #include <linux/clk-provider.h>
58 #include <soc/qcom/kryo-l2-accessors.h>
60 #include "clk-alpha-pll.h"
61 #include "clk-regmap.h"
209 	u32 mask = GENMASK(cpuclk->width - 1, 0);  in clk_cpu_8996_mux_get_parent()
212 	regmap_read(clkr->regmap, cpuclk->reg, &val);  in clk_cpu_8996_mux_get_parent()
213 	val >>= cpuclk->shift;  in clk_cpu_8996_mux_get_parent()
222 	u32 mask = GENMASK(cpuclk->width + cpuclk->shift - 1, cpuclk->shift);  in clk_cpu_8996_mux_set_parent()
226 	val <<= cpuclk->shift;  in clk_cpu_8996_mux_set_parent()
228 	return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);  in clk_cpu_8996_mux_set_parent()
235 	struct clk_hw *parent = cpuclk->pll;  in clk_cpu_8996_mux_determine_rate()
237 	if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) {  in clk_cpu_8996_mux_determine_rate()
238 		if (req->rate < (DIV_2_THRESHOLD / 2))  in clk_cpu_8996_mux_determine_rate()
239 			return -EINVAL;  in clk_cpu_8996_mux_determine_rate()
241 		parent = cpuclk->pll_div_2;  in clk_cpu_8996_mux_determine_rate()
244 	req->best_parent_rate = clk_hw_round_rate(parent, req->rate);  in clk_cpu_8996_mux_determine_rate()
245 	req->best_parent_hw = parent;  in clk_cpu_8996_mux_determine_rate()
465 		ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);  in cpu_clk_notifier_cb()
469 		if (cnd->new_rate < DIV_2_THRESHOLD)  in cpu_clk_notifier_cb()
470 			ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,  in cpu_clk_notifier_cb()
473 			ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,  in cpu_clk_notifier_cb()
488 	struct device *dev = &pdev->dev;  in qcom_cpu_clk_msm8996_driver_probe()
493 		return -ENOMEM;  in qcom_cpu_clk_msm8996_driver_probe()
509 	data->hws[0] = &pwrcl_pmux.clkr.hw;  in qcom_cpu_clk_msm8996_driver_probe()
510 	data->hws[1] = &perfcl_pmux.clkr.hw;  in qcom_cpu_clk_msm8996_driver_probe()
511 	data->num = 2;  in qcom_cpu_clk_msm8996_driver_probe()
522 	{ .compatible = "qcom,msm8996-apcc" },
531 		.name = "qcom-msm8996-apcc",
537 MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver");