clk/qcom/clk-alpha-pll.h

1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
8 #include "clk-regmap.h"
50 #define VCO(a, b, c) { \  macro
57  * struct clk_alpha_pll - phase locked loop (PLL)
58  * @offset: base address of registers
59  * @vco_table: array of VCO settings
64 	u32 offset;  member
78  * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
79  * @offset: base address of registers
81  * @width: width of post-divider
82  * @post_div_shift: shift to differentiate between odd & even post-divider
83  * @post_div_table: table with PLL odd and even post-divider settings
84  * @num_post_div: Number of PLL post-divider settings
89 	u32 offset;  member