Lines Matching +full:vco +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include "clk-alpha-pll.h"
15 #define PLL_MODE(p) ((p)->offset + 0x0)
34 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
36 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
37 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
39 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
41 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
47 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
48 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
50 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
51 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
52 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
53 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
54 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
55 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
56 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
57 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
58 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
150 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
153 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
167 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
169 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
173 for (count = 100; count > 0; count--) { in wait_for_pll()
174 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
186 return -ETIMEDOUT; in wait_for_pll()
215 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_alpha_pll_configure()
216 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_alpha_pll_configure()
217 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); in clk_alpha_pll_configure()
221 config->config_ctl_hi_val); in clk_alpha_pll_configure()
224 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); in clk_alpha_pll_configure()
226 val = config->main_output_mask; in clk_alpha_pll_configure()
227 val |= config->aux_output_mask; in clk_alpha_pll_configure()
228 val |= config->aux2_output_mask; in clk_alpha_pll_configure()
229 val |= config->early_output_mask; in clk_alpha_pll_configure()
230 val |= config->pre_div_val; in clk_alpha_pll_configure()
231 val |= config->post_div_val; in clk_alpha_pll_configure()
232 val |= config->vco_val; in clk_alpha_pll_configure()
233 val |= config->alpha_en_mask; in clk_alpha_pll_configure()
234 val |= config->alpha_mode_mask; in clk_alpha_pll_configure()
236 mask = config->main_output_mask; in clk_alpha_pll_configure()
237 mask |= config->aux_output_mask; in clk_alpha_pll_configure()
238 mask |= config->aux2_output_mask; in clk_alpha_pll_configure()
239 mask |= config->early_output_mask; in clk_alpha_pll_configure()
240 mask |= config->pre_div_mask; in clk_alpha_pll_configure()
241 mask |= config->post_div_mask; in clk_alpha_pll_configure()
242 mask |= config->vco_mask; in clk_alpha_pll_configure()
246 if (pll->flags & SUPPORTS_FSM_MODE) in clk_alpha_pll_configure()
257 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_enable()
263 if (pll->flags & SUPPORTS_OFFLINE_REQ) in clk_alpha_pll_hwfsm_enable()
266 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); in clk_alpha_pll_hwfsm_enable()
282 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_hwfsm_disable()
286 if (pll->flags & SUPPORTS_OFFLINE_REQ) { in clk_alpha_pll_hwfsm_disable()
287 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
298 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_hwfsm_disable()
312 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in pll_is_enabled()
336 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_enable()
352 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
359 * de-asserting the reset. in clk_alpha_pll_enable()
364 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
373 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in clk_alpha_pll_enable()
387 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_disable()
398 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
405 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); in clk_alpha_pll_disable()
445 const struct pll_vco *v = pll->vco_table; in alpha_pll_find_vco()
446 const struct pll_vco *end = v + pll->num_vco; in alpha_pll_find_vco()
449 if (rate >= v->min_freq && rate <= v->max_freq) in alpha_pll_find_vco()
463 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_alpha_pll_recalc_rate()
465 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_recalc_rate()
467 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); in clk_alpha_pll_recalc_rate()
469 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), in clk_alpha_pll_recalc_rate()
473 a = low & GENMASK(alpha_width - 1, 0); in clk_alpha_pll_recalc_rate()
477 a >>= alpha_width - ALPHA_BITWIDTH; in clk_alpha_pll_recalc_rate()
489 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); in __clk_alpha_pll_update_latch()
492 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, in __clk_alpha_pll_update_latch()
510 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); in __clk_alpha_pll_update_latch()
530 if (!is_enabled(&pll->clkr.hw) || in clk_alpha_pll_update_latch()
531 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) in clk_alpha_pll_update_latch()
542 const struct pll_vco *vco; in __clk_alpha_pll_set_rate() local
547 vco = alpha_pll_find_vco(pll, rate); in __clk_alpha_pll_set_rate()
548 if (pll->vco_table && !vco) { in __clk_alpha_pll_set_rate()
549 pr_err("%s: alpha pll not in a valid vco range\n", in __clk_alpha_pll_set_rate()
551 return -EINVAL; in __clk_alpha_pll_set_rate()
554 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in __clk_alpha_pll_set_rate()
557 a <<= alpha_width - ALPHA_BITWIDTH; in __clk_alpha_pll_set_rate()
560 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); in __clk_alpha_pll_set_rate()
562 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in __clk_alpha_pll_set_rate()
564 if (vco) { in __clk_alpha_pll_set_rate()
565 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
567 vco->val << PLL_VCO_SHIFT); in __clk_alpha_pll_set_rate()
570 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in __clk_alpha_pll_set_rate()
599 if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) in clk_alpha_pll_round_rate()
602 min_freq = pll->vco_table[0].min_freq; in clk_alpha_pll_round_rate()
603 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; in clk_alpha_pll_round_rate()
613 * of [-0.5, 0.5). in alpha_huayra_pll_calc_rate()
615 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_calc_rate()
616 l -= 1; in alpha_huayra_pll_calc_rate()
645 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value in alpha_huayra_pll_round_rate()
648 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) in alpha_huayra_pll_round_rate()
662 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_huayra_recalc_rate()
663 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_recalc_rate()
666 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); in alpha_pll_huayra_recalc_rate()
674 * M is a signed number (-128 to 127) and N is unsigned in alpha_pll_huayra_recalc_rate()
675 * (0 to 255). M/N has to be within +/-0.5. in alpha_pll_huayra_recalc_rate()
678 * range [-0.5, 0.5). in alpha_pll_huayra_recalc_rate()
692 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { in alpha_pll_huayra_recalc_rate()
693 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; in alpha_pll_huayra_recalc_rate()
696 rate -= tmp; in alpha_pll_huayra_recalc_rate()
717 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in alpha_pll_huayra_set_rate()
720 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); in alpha_pll_huayra_set_rate()
730 return -EBUSY; in alpha_pll_huayra_set_rate()
733 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
739 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_huayra_set_rate()
740 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_huayra_set_rate()
743 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
746 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in alpha_pll_huayra_set_rate()
778 return trion_pll_is_enabled(pll, pll->clkr.regmap); in clk_trion_pll_is_enabled()
784 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_enable()
821 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_disable()
857 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in clk_trion_pll_recalc_rate()
858 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac); in clk_trion_pll_recalc_rate()
916 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_recalc_rate()
947 if (pll->width == 2) in clk_alpha_pll_postdiv_round_rate()
953 pll->width, CLK_DIVIDER_POWER_OF_TWO); in clk_alpha_pll_postdiv_round_rate()
963 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); in clk_alpha_pll_postdiv_round_ro_rate()
966 ctl &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_round_ro_rate()
981 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ in clk_alpha_pll_postdiv_set_rate()
982 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; in clk_alpha_pll_postdiv_set_rate()
984 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_set_rate()
1007 if (config->l) in clk_fabia_pll_configure()
1008 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_fabia_pll_configure()
1010 if (config->alpha) in clk_fabia_pll_configure()
1011 regmap_write(regmap, PLL_FRAC(pll), config->alpha); in clk_fabia_pll_configure()
1013 if (config->config_ctl_val) in clk_fabia_pll_configure()
1015 config->config_ctl_val); in clk_fabia_pll_configure()
1017 if (config->config_ctl_hi_val) in clk_fabia_pll_configure()
1019 config->config_ctl_hi_val); in clk_fabia_pll_configure()
1021 if (config->user_ctl_val) in clk_fabia_pll_configure()
1022 regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val); in clk_fabia_pll_configure()
1024 if (config->user_ctl_hi_val) in clk_fabia_pll_configure()
1026 config->user_ctl_hi_val); in clk_fabia_pll_configure()
1028 if (config->test_ctl_val) in clk_fabia_pll_configure()
1030 config->test_ctl_val); in clk_fabia_pll_configure()
1032 if (config->test_ctl_hi_val) in clk_fabia_pll_configure()
1034 config->test_ctl_hi_val); in clk_fabia_pll_configure()
1036 if (config->post_div_mask) { in clk_fabia_pll_configure()
1037 mask = config->post_div_mask; in clk_fabia_pll_configure()
1038 val = config->post_div_val; in clk_fabia_pll_configure()
1054 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_enable()
1111 struct regmap *regmap = pll->clkr.regmap; in alpha_pll_fabia_disable()
1142 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); in alpha_pll_fabia_recalc_rate()
1143 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); in alpha_pll_fabia_recalc_rate()
1165 return -EINVAL; in alpha_pll_fabia_set_rate()
1168 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_fabia_set_rate()
1169 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); in alpha_pll_fabia_set_rate()
1177 const struct pll_vco *vco; in alpha_pll_fabia_prepare() local
1186 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in alpha_pll_fabia_prepare()
1194 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); in alpha_pll_fabia_prepare()
1195 if (!vco) { in alpha_pll_fabia_prepare()
1196 pr_err("%s: alpha pll not in a valid vco range\n", name); in alpha_pll_fabia_prepare()
1197 return -EINVAL; in alpha_pll_fabia_prepare()
1200 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + in alpha_pll_fabia_prepare()
1201 pll->vco_table[0].max_freq) * 54, 100); in alpha_pll_fabia_prepare()
1205 return -EINVAL; in alpha_pll_fabia_prepare()
1214 return -EINVAL; in alpha_pll_fabia_prepare()
1217 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), cal_l); in alpha_pll_fabia_prepare()
1258 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); in clk_alpha_pll_postdiv_fabia_recalc_rate()
1262 val >>= pll->post_div_shift; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1263 val &= BIT(pll->width) - 1; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1265 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1266 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1267 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1279 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_recalc_rate()
1284 val >>= pll->post_div_shift; in clk_trion_pll_postdiv_recalc_rate()
1287 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_recalc_rate()
1288 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1289 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1303 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1304 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_trion_pll_postdiv_round_rate()
1312 struct regmap *regmap = pll->clkr.regmap; in clk_trion_pll_postdiv_set_rate()
1316 for (i = 0; i < pll->num_post_div; i++) { in clk_trion_pll_postdiv_set_rate()
1317 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1318 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1340 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1341 pll->width, CLK_DIVIDER_ROUND_CLOSEST); in clk_alpha_pll_postdiv_fabia_round_rate()
1352 * no-operation. in clk_alpha_pll_postdiv_fabia_set_rate()
1354 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in clk_alpha_pll_postdiv_fabia_set_rate()
1362 for (i = 0; i < pll->num_post_div; i++) { in clk_alpha_pll_postdiv_fabia_set_rate()
1363 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1364 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
1369 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), in clk_alpha_pll_postdiv_fabia_set_rate()
1370 (BIT(pll->width) - 1) << pll->post_div_shift, in clk_alpha_pll_postdiv_fabia_set_rate()
1371 val << pll->post_div_shift); in clk_alpha_pll_postdiv_fabia_set_rate()
1382 * clk_lucid_pll_configure - configure the lucid pll
1391 if (config->l) in clk_trion_pll_configure()
1392 regmap_write(regmap, PLL_L_VAL(pll), config->l); in clk_trion_pll_configure()
1396 if (config->alpha) in clk_trion_pll_configure()
1397 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); in clk_trion_pll_configure()
1399 if (config->config_ctl_val) in clk_trion_pll_configure()
1401 config->config_ctl_val); in clk_trion_pll_configure()
1403 if (config->config_ctl_hi_val) in clk_trion_pll_configure()
1405 config->config_ctl_hi_val); in clk_trion_pll_configure()
1407 if (config->config_ctl_hi1_val) in clk_trion_pll_configure()
1409 config->config_ctl_hi1_val); in clk_trion_pll_configure()
1411 if (config->user_ctl_val) in clk_trion_pll_configure()
1413 config->user_ctl_val); in clk_trion_pll_configure()
1415 if (config->user_ctl_hi_val) in clk_trion_pll_configure()
1417 config->user_ctl_hi_val); in clk_trion_pll_configure()
1419 if (config->user_ctl_hi1_val) in clk_trion_pll_configure()
1421 config->user_ctl_hi1_val); in clk_trion_pll_configure()
1423 if (config->test_ctl_val) in clk_trion_pll_configure()
1425 config->test_ctl_val); in clk_trion_pll_configure()
1427 if (config->test_ctl_hi_val) in clk_trion_pll_configure()
1429 config->test_ctl_hi_val); in clk_trion_pll_configure()
1431 if (config->test_ctl_hi1_val) in clk_trion_pll_configure()
1433 config->test_ctl_hi1_val); in clk_trion_pll_configure()
1450 * The TRION PLL requires a power-on self-calibration which happens when the
1460 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), ®val); in __alpha_pll_trion_prepare()
1499 return -EINVAL; in alpha_pll_trion_set_rate()
1502 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); in alpha_pll_trion_set_rate()
1503 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); in alpha_pll_trion_set_rate()
1506 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in alpha_pll_trion_set_rate()
1513 regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val); in alpha_pll_trion_set_rate()
1516 return -EINVAL; in alpha_pll_trion_set_rate()
1520 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), in alpha_pll_trion_set_rate()