1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/pxa-clock.h>
16 #include "clk-pxa.h"
21 #define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
22 #define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
23 #define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
24 #define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
25 #define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
26 #define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
27 #define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
28 #define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
29 #define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
30 #define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
31 #define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
32 #define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
33 #define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
34 #define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
62 	if (!pclk->is_in_low_power || pclk->is_in_low_power())  in cken_recalc_rate()
63 		fix = &pclk->lp;  in cken_recalc_rate()
65 		fix = &pclk->hp;  in cken_recalc_rate()
66 	__clk_hw_set_clk(&fix->hw, hw);  in cken_recalc_rate()
67 	return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate);  in cken_recalc_rate()
78 	if (!pclk->is_in_low_power)  in cken_get_parent()
80 	return pclk->is_in_low_power() ? 0 : 1;  in cken_get_parent()
105 		pxa_clk->is_in_low_power = clks[i].is_in_low_power;  in clk_pxa_cken_init()
106 		pxa_clk->lp = clks[i].lp;  in clk_pxa_cken_init()
107 		pxa_clk->hp = clks[i].hp;  in clk_pxa_cken_init()
108 		pxa_clk->gate = clks[i].gate;  in clk_pxa_cken_init()
109 		pxa_clk->gate.lock = &pxa_clk_lock;  in clk_pxa_cken_init()
112 					     &pxa_clk->hw, &cken_mux_ops,  in clk_pxa_cken_init()
113 					     &pxa_clk->hw, &cken_rate_ops,  in clk_pxa_cken_init()
114 					     &pxa_clk->gate.hw, &clk_gate_ops,  in clk_pxa_cken_init()
156 	unsigned int clkcfg = freq->clkcfg;  in pxa2xx_cpll_change()
167 	if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(freq->membus_khz)) {  in pxa2xx_cpll_change()
169 		preset_mdrefr |= mdrefr_dri(freq->membus_khz);  in pxa2xx_cpll_change()
173 		mdrefr_dri(freq->membus_khz);  in pxa2xx_cpll_change()
179 	if (freq->div2) {  in pxa2xx_cpll_change()
187 	writel(freq->cccr, cccr);  in pxa2xx_cpll_change()
210 	int i, closest_below = -1, closest_above = -1;  in pxa2xx_determine_rate()
215 		if (rate == req->rate)  in pxa2xx_determine_rate()
217 		if (rate < req->min_rate)  in pxa2xx_determine_rate()
219 		if (rate > req->max_rate)  in pxa2xx_determine_rate()
221 		if (rate <= req->rate)  in pxa2xx_determine_rate()
223 		if ((rate >= req->rate) && (closest_above == -1))  in pxa2xx_determine_rate()
227 	req->best_parent_hw = NULL;  in pxa2xx_determine_rate()
230 		rate = req->rate;  in pxa2xx_determine_rate()
236 		pr_debug("%s(rate=%lu) no match\n", __func__, req->rate);  in pxa2xx_determine_rate()
237 		return -EINVAL;  in pxa2xx_determine_rate()
240 	pr_debug("%s(rate=%lu) rate=%lu\n", __func__, req->rate, rate);  in pxa2xx_determine_rate()
241 	req->rate = rate;  in pxa2xx_determine_rate()